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Simultaneous Power and Thermal Integrity Driven Via Stapling in 3D ICs Hao Yu, Joanna Ho and Lei He Electrical Engineering Dept. UCLA Partially supported by NSF and UC-MICRO fund from Intel

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2 New Solution for High-performance Integration n 2D SoC has limited device density and interconnect performance (delay) n Potential solution: 3D Integration l Fabrication Technologies: Chip-level Wafer Bonding or Die-level Silicon Epitaxial Growth n Extra challenges: thermal integrity and power integrity

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3 Thermal Challenge in 3D ICs n Inter-layer dielectrics are poor thermal conductors l the temperature of each die increases along third dimension, where the heat sink is on the top n Vertical vias are good thermal conductors l They can be used as thermal vias to remove the heat from each die 40c 70c 100c 130c 160c n High temperature affects interconnect and device reliability and brings variations to timing

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4 Power Delivery Challenge in 3D ICs n Vertical vias can minimize the returned current path and hence loop inductance l They can be used as power vias to reduce the voltage bounce for each P/G plane n The voltage bounce is significant in P/G planes at the bottom due to resonance n Large voltage bounce affects the performance of I/Os

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5 Via Planning Problem in 3D IC n Previous work (thermal via planning) l Iterative via planning during placement [Goplen-Sapatnekar:ISPD’05] l Alternating-direction via planning during routing [Zhang-Cong:ICCAD’05] l Both use steady-state thermal analysis and ignore variant thermal power l Both ignore that the vertical via can be also designed to remove the voltage bounce in power supply n Motivation l Staple vias from the top heat-sink to the bottom P/G planes u remove heat in silicon die and reduce voltage bounce in package plane l Too many? -> signal routing congestion l Too few? -> reliability by current density n Primary contributions of our work l Formulate a levelized via stapling to simultaneously minimize both temperature hotspot and voltage bounce l Develop an efficient sensitivity-driven optimization with use of structured and parameterized macromodel

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6 Outline n Modeling and Problem Formulation n Integrity Analysis and Sensitivity based Optimization n Experimental Results n Conclusions

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7 Electric and Thermal Duality Temperature Voltage state variables (x(t)) Thermal-Power Input Current sources (u(t)) Thermal conductance Electrical conductance (G) Thermal capacitanceElectrical capacitance (C) n Both electric and thermal systems can be described in MNA (modified nodal analysis)

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8 Two Distributed Networks for 3D IC n All device/dielectric layers and power planes are discretized into tiles n A distributed electrical RLC model for power/ground plane n A distributed thermal RC model for device/dielectric layer n Each via is modeled by a RC pair

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9 Thermal Model and Analysis n Steady-state thermal model and analysis l Tiles connected by thermal resistance l Heat sources modeled as time-invariant current sources l Steady-state temperature can be obtained by directly solving a time-invariant linear equation n Transient thermal model and analysis l Tiles connected by thermal resistance and capacitance l Heat sources modeled as time-variant current sources l Transient temperature can be obtained by directly solving a time- variant linear equation

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10 Need of Transient Thermal Modeling n Time-variant workload and dynamic power management introduce temporal and spatial thermal power variation l Thermal power is the runtime average of cycle-accurate power over thermal time-constant l Thermal power decides temperature n Steady-state analysis needs to assume a maximum thermal power simultaneously for all regions l But it rarely happens and hence can result in an over-design n Direct transient analysis is accurate but time-consuming l It calls for more accurate yet efficient transient thermal modeling during the design automation

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11 Need of Simultaneous Thermal/Power Co-Design n Temperature hotspots usually distribute differently from voltage bounce l A thermal integrity map tends to result in a uniform via stapling pattern l A power integrity map tends to result in a biased via stapling pattern in center n Considering thermal and power integrity separately may also lead to over-design

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12 Problem Formulation n It can be efficiently solved by a sensitivity based optmization l The sensitivity is calculated from a structured and parameterized macromodel n A levelized via stapling is used Each level has a different via density Di D0D1D2 Via Stapling n Minimize via number under thermal/power integrity constraint l Di levelized via density l ni via number at different level l Vmax power integrity constraint l Tmax thermal integrity constraint l Dmax congestion from signal via l Dmin current density constraints

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13 Outline n Modeling and Problem Formulation n Integrity Analysis and Sensitivity based Optimization n Experimental Results n Conclusions

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14 Parameterized System Equation The levelized stapling pattern is described by adjacent matrix X X(2,6)= n Via conductance gi and capacitance ci are both proportional to the area Di or density (Di/a) (a is unit via area) Both Di and Xi are parametrically added into the nominal MNA equation

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15 Separation of Nominal and Sensitivity n Expanded system is reorganized into a lower-triangular-block system Expand state variables x(D 1,…D K,s) by Taylor expansion w.r.t. to D i [Li-Pileggi:ICCAD’05] l Construct a new state variables by nominal values and sensitivities n Since system size is enlarged, we can reduce it by model reduction

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16 Macromodel by Model Reduction large size … Small but dense small size n Model reduction can reduce model size and preserve accuracy by matching moments of inputs [Odabasioglu-Celik-Pileggi:TCAD’98] l The projection above is non-structured, and will mess the nominal values and their sensitivities again l This can be solved by a structure-preserving reduction [Yu- Tan-He:BMAS’05, Yu-Shi-He:DAC’06] project

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17 Structured Projection (I) n Block-diagonally partition the flat projection matrix according to the size of nominal state-variable and sensitivity n Structured projection can result in a reduced system with preserved structure l Nominal values and sensitivities are still separated after reduction There is only one LU-factorization of the reduced G 0 in diagonal

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18 Time-domain Analysis n Generated sensitivities can be used in any gradient based optimization n Nominal response and sensitivity can be solved separately and efficiently with BE in time-domain We call this method as SP-MACRO n Direct sensitivity calculation

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19 Sensitivity based Optimization n Structured and parameterized reduction provides an efficient calculation of both nominal value and sensitivity The via density vector D can be efficiently updated during each iteration l Normalized sensitivity according to both temperature and voltage (T/V) sensitivities n Further speedup: adjoint Lagrangian method similar to [Visweswariah-Conn-Haring:TCAD’00] n Via optimization flow Calculate T/V nominal+sensitivity Check Integrity Constraints Update Density Vector

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20 Outline n Modeling and Problem Formulation n Integrity Analysis and Sensitivity based Optimization n Experimental Results n Conclusions

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21 Experiment Settings SiliconCopperDielectric SigmaNA59.6x 10^6S/mNA EpsilonNA 3.3 MuNA 1.0 Kapa_r100W/mK400W/mK50W/mK Kapa_c1.75x10^6J/m^3K3.55x10^6J/m^3KNA n A modest 3D stacking layersizematerialnumbermesh heat-sink2cm x2cmx1mmcopper1RC device-layer1cmx1cmx4umsilicon2RC inter-layer1cmx1cmx1umdielectric 2RC P/G plane2cmx2cm x10umcopper2RLC

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22 Accuracy of Reduced Macromodel n Transient voltage responses of exact and MACRO models at ports 1 and 5 in one P/G plane with step-response input l The responses of macromodels are visually identical to those exact models but with >100 speedup

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23 Temperature/Voltage Reduction during OPT n The T/V are both decreased iteratively l The allocated via results in a design meeting the targeted temperature 52C and the voltage bounce 0.2V

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24 Steady-state vs. Transient n Transient thermal analysis reduces via by 11.5% on average compared to using steady thermal analysis n Our SP-Macro results in an efficient transient analysis that reduces runtime by 155X compared to the direct steady-state analysis Total tile# Level vector Steady-stateTran by SP-MACRO Solve dc (s) Total via Redu Ckt(s) Solve BE(s) Total via Saving ratio 6200, % 21400,1, % 79000,1,2, % ,1,2,3, % ,1,2,3,4,5NA NA

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25 Sequential vs. Simultaneous Total tile#Seq.Sim % % % % 55680NA144998NA n Simultaneous optimization reduces via by 34% on average compared to the sequential optimization Opt- method Level P/G-only / Thermal- only / Sim n Comparisons of via distribution at different levels for ckt (27740)

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26 Conclusions n Vertical vias play a critical role in 3D IC design n A simultaneous thermal and power integrity driven via planning l It saves via number by 34% on average compared to a sequential design n A structured and parameterized macromodel can be efficiently employed during the design optimization n This method can be further extended l 3D signal and P/G routing l Performance driven 3D design

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