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**Simultaneous Power and Thermal Integrity Driven Via Stapling in 3D ICs**

Hao Yu, Joanna Ho and Lei He Electrical Engineering Dept. UCLA My presentation topic is about a Simultaneous Power and Thermal Integrity Driven Via Stapling in 3D ICs. We are partially supported by NSF and UC-Micro fund from Intel. Partially supported by NSF and UC-MICRO fund from Intel Research Projects Overview

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**New Solution for High-performance Integration**

2D SoC has limited device density and interconnect performance (delay) 2D SoC is limited by the device density and interconnect performance such as delay. One promising solution is to use the third dimension to further pack devices and reduce interconnect delay. The enabling technology for such a 3D IC includes: Chip-level Wafer Bonding or Die-level Silicon Epitaxial Growth. For the die level 3D integration, a conceptual diagram for 3D IC is shown below. It includes heat sink on top, active device layer, inter-layer dielectric, inter-layer via and power supply planes on bottom. Such a integration also brings extra challenges. As discussed in this paper, we to need consider both thermal and power integrities in design. Potential solution: 3D Integration Fabrication Technologies: Chip-level Wafer Bonding or Die-level Silicon Epitaxial Growth Extra challenges: thermal integrity and power integrity Research Projects Overview

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**Thermal Challenge in 3D ICs**

Inter-layer dielectrics are poor thermal conductors the temperature of each die increases along third dimension, where the heat sink is on the top 40c 70c 100c 130c 160c Because the dielectric layer are poor thermal conductors, Temperature of each die increases along third dimension as shown in this figure. Heat sink is on the top… High temperature has already been an issue for 2D chips. It could affect interconnect and device reliability and lead to variations to timing. Therefore, a 3D IC design tool has to consider the thermal problem. One solution is to staple good thermal conductors such as inter-layer vias can remove the heat. High temperature affects interconnect and device reliability and brings variations to timing Vertical vias are good thermal conductors They can be used as thermal vias to remove the heat from each die Research Projects Overview

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**Power Delivery Challenge in 3D ICs**

The voltage bounce is significant in P/G planes at the bottom due to resonance In addition, note that The voltage bounce is significant in P/G planes at the bottom due to resonance. Large voltage bounce affects the performances of I/Os. Interestingly, because Vertical vias can minimize the returned current path and hence loop inductance They can be also used as power vias to reduce the voltage bounce for each P/G plane. Large voltage bounce affects the performance of I/Os Vertical vias can minimize the returned current path and hence loop inductance They can be used as power vias to reduce the voltage bounce for each P/G plane Research Projects Overview

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**Via Planning Problem in 3D IC**

Motivation Staple vias from the top heat-sink to the bottom P/G planes remove heat in silicon die and reduce voltage bounce in package plane Too many? -> signal routing congestion Too few? -> reliability by current density Previous work (thermal via planning) Iterative via planning during placement [Goplen-Sapatnekar:ISPD’05] Alternating-direction via planning during routing [Zhang-Cong:ICCAD’05] Both use steady-state thermal analysis and ignore variant thermal power Both ignore that the vertical via can be also designed to remove the voltage bounce in power supply Based on the above observations, we propose to Staple vias from the top heat-sink to the bottom P/G planes. As a result, it can remove heat in silicon die and reduce voltage bounce in package plane. There are following existing works about via planning in 3D IC. Goplen proposed an iterative via planning during placement. Zhang proposed an alternating direction via planning during routing. These two methods both use a steady-state analysis and assume a maximum-thermal power. As shown by our paper, they may lead to over-design, i.e., unnecessary number of vias. In this paper, we propose to minimize a thermal violation integral with the constraint of routing congestion. The solution algorithm is based on an efficient sensitivity-driven sequential programming with the use of macromodel. Our key contribution is to apply macromodel based transient thermal analysis for via planning to avoid over design. Primary contributions of our work Formulate a levelized via stapling to simultaneously minimize both temperature hotspot and voltage bounce Develop an efficient sensitivity-driven optimization with use of structured and parameterized macromodel Research Projects Overview

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**Modeling and Problem Formulation **

Outline Modeling and Problem Formulation Integrity Analysis and Sensitivity based Optimization Experimental Results Conclusions In the following I’ll first review the background of thermal analysis and then present out problem formulation. Research Projects Overview

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**Electric and Thermal Duality**

Temperature Voltage state variables (x(t)) Thermal-Power Input Current sources (u(t)) Thermal conductance Electrical conductance (G) Thermal capacitance Electrical capacitance (C) Both electric and thermal systems can be described in MNA (modified nodal analysis) Let’s first review the well-known thermal-electrical duality. The table shows that the temperature corresponds to the electrical voltage response, and the thermal power corresponds to the input current sources. In addition, there exist the corresponding thermal conductance and capacitance. Animation As a result, the thermal system could be also described by MNA based state equation in both time and frequency domain. In addition, as shown later on, because the via conductance and capacitance are both proportional to the size or the via density D,they can be parametrically added into the MNA equation. Research Projects Overview

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**Two Distributed Networks for 3D IC**

All device/dielectric layers and power planes are discretized into tiles A distributed electrical RLC model for power/ground plane A distributed thermal RC model for device/dielectric layer Each via is modeled by a RC pair Moreover, we use two distributed networks to model 3D IC. A distributed electrical RLC model for power/ground plane, and a distributed thermal RC model for device/dielectric layer. In addition, each via is modeled by a RC pair. All device/dielectric layers and power planes are discretized into tiles. Research Projects Overview

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**Thermal Model and Analysis**

Steady-state thermal model and analysis Tiles connected by thermal resistance Heat sources modeled as time-invariant current sources Steady-state temperature can be obtained by directly solving a time-invariant linear equation Transient thermal model and analysis Tiles connected by thermal resistance and capacitance Heat sources modeled as time-variant current sources Transient temperature can be obtained by directly solving a time-variant linear equation Let’s further discuss details of thermal model and analysis. In the steady-state thermal analysis, the tiles are connected through thermal resistances. The heat sources are modeled as time-invariant current sources. Then steady-state temperature can be obtained by directly solving a time-invariant linear equation. On the other hand, in the transient thermal analysis, the tiles are connected through thermal resistances and capacitances. The heat sources are modeled as time-variant current sources. Then transient temperature can be obtained by directly solving a time-variant linear equation. Research Projects Overview

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**Need of Transient Thermal Modeling**

Time-variant workload and dynamic power management introduce temporal and spatial thermal power variation Thermal power is the runtime average of cycle-accurate power over thermal time-constant Thermal power decides temperature Steady-state analysis needs to assume a maximum thermal power simultaneously for all regions But it rarely happens and hence can result in an over-design Why do we need transient thermal analysis? This is because time-variant workload and dynamic power management introduce temporal and spatial thermal power variation, Where thermal power is the runtime average over the thermal time-constant of cycle-accurate power, and it decides the temperature. As a result, the steady-state analysis has to assume a maximum thermal power simultaneously for all regions But it rarely happens and hence can result in an over-design. On the other hand, a transient thermal analysis is accurate but it is also time-consuming. As such, it calls for more accurate yet efficient transient thermal simulation during the design automation Direct transient analysis is accurate but time-consuming It calls for more accurate yet efficient transient thermal modeling during the design automation Research Projects Overview

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**Need of Simultaneous Thermal/Power Co-Design**

Temperature hotspots usually distribute differently from voltage bounce A thermal integrity map tends to result in a uniform via stapling pattern A power integrity map tends to result in a biased via stapling pattern in center In addition to use a transient analysis, we also propose a Simultaneous Thermal/Power Co-Design. As shown by simulation in this figure, Temperature hotspots usually distribute differently from voltage bounce, Accordingly, a power integrity map tends to result in a biased via stapling pattern in center, And A thermal integrity map tends to result in a uniform via stapling pattern. As a result, Considering thermal and power integrity separately may also lead to over-design. Considering thermal and power integrity separately may also lead to over-design Research Projects Overview

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**Problem Formulation A levelized via stapling is used**

Each level has a different via density Di Minimize via number under thermal/power integrity constraint Di levelized via density ni via number at different level Vmax power integrity constraint Tmax thermal integrity constraint Dmax congestion from signal via Dmin current density constraints Therefore, to simultaneously consider the power and thermal integrities with different stapling patterns, We propose a levelized via stamping. As shown by this figure, for a level—0 stapling, the vias are only allocated in the center. And for a level-1 stapling, the plane is first divided into 4 sub planes, and vias are then allocated into 4 centers of sub lanes. Note that Each level has a different via density Di. Correspondingly, we give the problem formulation as follows. Our via planning problem is to find a via density vector D to minimize the total via number. It is constrained by the thermal integrity for each die and power integrity for power plane. In addition, we also consider the constraints of signal congestion and reliability for current density. This problem can be efficiently solved by the sensitivity based method, Where The sensitivity is calculated from the structured and parameterized macromodel. It can be efficiently solved by a sensitivity based optmization The sensitivity is calculated from a structured and parameterized macromodel Research Projects Overview

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**Modeling and Problem Formulation **

Outline Modeling and Problem Formulation Integrity Analysis and Sensitivity based Optimization Experimental Results Conclusions Therefore, next I will talk about the structured and parameterized model reduction to generate macromodel Research Projects Overview

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**Parameterized System Equation**

The levelized stapling pattern is described by adjacent matrix X 1 - -1 X(2,6)= Both Di and Xi are parametrically added into the nominal MNA equation 1 2 3 4 5 6 7 8 Via conductance gi and capacitance ci are both proportional to the area Di or density (Di/a) (a is unit via area) To generate sensitivity, we need first parameterize the system. In this problem, we use two parameters: levelized stapling pattern and the via density for each pattern. The levelized stapling pattern could be described by an adjacent matrix X. For example, if we insert one via in between node 2 and node 6, the corresponding adjacent matrix can be described by X(2,6) as shown in right. In addition, because via conductance and capacitance are both proportional to size or density, one density parameter Di is used for each stapling pattern. As a result, both Di and Xi are parametrically added into the nominal MNA equation below. Note that the state variable here is a total voltage or temperature response. For the purpose of design automation, we need to separate sensitivity from the nominal value. Research Projects Overview

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**Separation of Nominal and Sensitivity**

Expand state variables x(D1,…DK,s) by Taylor expansion w.r.t. to Di [Li-Pileggi:ICCAD’05] Construct a new state variables by nominal values and sensitivities Expanded system is reorganized into a lower-triangular-block system Similar to handle variations in this paper, we first expand the state variable x by Taylor expansion w.r.t. to the via density parameter Di. Then construct an expanded state variables by nominal value and sensitivity w.r.t. Di, Accordingly, the expanded system can be reorganized into a lower block-triangular system according to the expansion order. Figure in right shows the lower-triangular block structure for G_ap. C_ap has a similar structure as well. The system size is enlarged and needs to be reduced. However, previous flat projection can not separate the nominal state variables and their sensitivities. we find that this can be solved by a structure-preserved projection as shown by the following slide. Since system size is enlarged, we can reduce it by model reduction Research Projects Overview

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**Macromodel by Model Reduction**

… … Small but dense project large size small size Model reduction can reduce model size and preserve accuracy by matching moments of inputs [Odabasioglu-Celik-Pileggi:TCAD’98] The projection above is non-structured, and will mess the nominal values and their sensitivities again This can be solved by a structure-preserving reduction [Yu-Tan-He:BMAS’05, Yu-Shi-He:DAC’06] As shown by this figure, constructing macromodel by model order reduction is simply to reduce the system size. One efficient method is to apply Krylov-subspace based projection method. The reduced model can preserve accuracy by matching moments of inputs. However, the existing reduction methods apply a non-structured flat projection. It does not preserve the block matrix structure such as sparsity. In addition, the reduced macromodel does not contains sensitivity information and hence can not be used for design automation efficiently. Research Projects Overview

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**Structured Projection (I)**

Block-diagonally partition the flat projection matrix according to the size of nominal state-variable and sensitivity Structured projection can result in a reduced system with preserved structure Nominal values and sensitivities are still separated after reduction There is only one LU-factorization of the reduced G0 in diagonal This can be done as follows. We first Block-diagonally partition a flat projection matrix according to the size of nominal variable and sensitivity. Then we apply the new projection matrix to project the original one, and the reduced system still has a separated nominal values and sensitivities. In addition, because the reduced model preserves the block triangular structure, There is only one LU-factorization of the reduced block in diagonal. Research Projects Overview

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Time-domain Analysis Nominal response and sensitivity can be solved separately and efficiently with BE in time-domain Direct sensitivity calculation Note that the time-domain transient response could be solved from the reduced system using backward-Euler integration. Because the reduced system preserve the block triangular structure, there is only one LU-factorization of the reduced nominal block in diagonal. Therefore, the nominal response, and sensitivity can be solved separately and efficiently. In addition, the generated sensitivities can be used in any gradient based optimization. We call this method as SP-MACRO. Generated sensitivities can be used in any gradient based optimization We call this method as SP-MACRO Research Projects Overview

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**Sensitivity based Optimization**

Via optimization flow Calculate T/V nominal+sensitivity Check Integrity Constraints Update Density Vector Structured and parameterized reduction provides an efficient calculation of both nominal value and sensitivity The via density vector D can be efficiently updated during each iteration Normalized sensitivity according to both temperature and voltage (T/V) sensitivities With the use of reduced model we can solve the first-order sensitivity as shown below. This procedure provides an efficient calculation of both nominal value and sensitivity. The calculated sensitivity can be further used to update the via density vector D during each iteration. In addition, note that the computation cost of sensitivity could be further reduced when an adjoint Lagrangian method is used for a system with large number of outputs than inputs. Further speedup: adjoint Lagrangian method similar to [Visweswariah-Conn-Haring:TCAD’00] Research Projects Overview

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**Modeling and Problem Formulation **

Outline Modeling and Problem Formulation Integrity Analysis and Sensitivity based Optimization Experimental Results Conclusions Finally, I will present the experiment results. Research Projects Overview

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**Experiment Settings A modest 3D stacking layer size material number**

mesh heat-sink 2cm x2cmx1mm copper 1 RC device-layer 1cmx1cmx4um silicon 2 inter-layer 1cmx1cmx1um dielectric P/G plane 2cmx2cm x10um RLC Silicon Copper Dielectric Sigma NA 59.6x 10^6S/m Epsilon 3.3 Mu 1.0 Kapa_r 100W/mK 400W/mK 50W/mK Kapa_c 1.75x10^6J/m^3K 3.55x10^6J/m^3K Here is the experiment settings. Read the slide… Research Projects Overview

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**Accuracy of Reduced Macromodel**

I will first show the accuracy of the reduced macromodel. Figure shows transient temperature responses of exact and SP-MACRO models at port 3, 18, and 58 of top layer with step-response input. The responses of macromodels are visually identical to those exact models. Transient voltage responses of exact and MACRO models at ports 1 and 5 in one P/G plane with step-response input The responses of macromodels are visually identical to those exact models but with >100 speedup Research Projects Overview

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**Temperature/Voltage Reduction during OPT**

The next figure shows the temperature reduction at selected location during the procedure of via-allocation by SQP. The procedure stops until that the transient temperature meets the targeted ceiling temperature 52C. The T/V are both decreased iteratively The allocated via results in a design meeting the targeted temperature 52C and the voltage bounce 0.2V Research Projects Overview

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**Steady-state vs. Transient**

Total tile# Level vector Steady-state Tran by SP-MACRO Solve dc (s) Total via Redu Ckt(s) BE(s) Saving ratio 620 0,1 4.06 176877 0.01 0.12 156154 11% 2140 0,1,2 26.37 187422 0.13 0.17 166971 7900 0,1,2,3 167.9 235484 1.22 0.86 206482 12% 27740 0,1,2,3,4 1243.7 239379 5.12 1.07 21184 55680 0,1,2,3,4,5 NA 15.87 3.65 216732 Transient thermal analysis reduces via by 11.5% on average compared to using steady thermal analysis Our SP-Macro results in an efficient transient analysis that reduces runtime by 155X compared to the direct steady-state analysis Research Projects Overview

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**Sequential vs. Simultaneous**

Simultaneous optimization reduces via by 34% on average compared to the sequential optimization Total tile# Seq. Sim. 620 176877 118020 -32% 2140 187422 127651 7900 235484 140433 -36% 27740 239379 143718 -37% 55680 NA 144998 Comparisons of via distribution at different levels for ckt (27740) In addition, we further compare the via distribution at different levels. The via pattern for P/G tends to concentrate in low level, but the via pattern for thermal only tends to concentrate in high level. On the other hand, the simultaneous stapling result in a uniform distribution of vias in all levels. Opt-method Level 1 2 3 4 P/G-only 76832 3410 1901 876 / Thermal-only 1157 43567 4007 79432 Sim. 67058 811 2500 2808 70541 Research Projects Overview

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**Vertical vias play a critical role in 3D IC design **

Conclusions Vertical vias play a critical role in 3D IC design A simultaneous thermal and power integrity driven via planning It saves via number by 34% on average compared to a sequential design A structured and parameterized macromodel can be efficiently employed during the design optimization We conclude as follows: Read the slide… This method can be further extended 3D signal and P/G routing Performance driven 3D design Research Projects Overview

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Announcements Be reading Chapters 9 and 10 HW 8 is due now.

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