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Published byOlivia Scott Modified over 4 years ago

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CMOS Adders for the Simplified MIPS Processor

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Specifications Needs to be fast: well under 1ns Needs to fit width of bitslice: 80λ Needs to be a reasonable length: <1500 λ Bitslice layout ~2000λ Total core area 3500λ x 3500λ

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Exploring the Options Static CMOS? –Easy to design and layout –Not very fast though Dynamic CMOS? –Not easy to design –Fast Dynamic CMOS Manchester Carry Chain

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Static CMOS Options Ripple Carry Adder –Simple to design and layout –Small footprint –Slow: Cout must propagate through all bits Carry Lookahead Adder –More complex design and carry logic –Significantly larger footprint –Faster than ripple carry

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Static CMOS Options cont. Carry Skip Adder –Faster than ripple carry adder –Slower than carry lookahead adder –Smaller footprint than carry lookahead adder –Larger footprint than ripple carry addder 16-bit carry skip adder with 4-bit carry lookahead groups

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Static CMOS Ripple Carry Adders Zhuang Full Adder –Fast: Transmission gates as MUXs –Low transistor count (22) leads to small layout –Already have it laid out, tested and speced

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Static CMOS Ripple Carry Adders Full Adder structure –Higher transistor count (28) –Larger transistors (8x for some pMOS!) –Carry out is no longer critical path

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Static CMOS Ripple Carry Adders Delay with no parasitics modeled Worst case determined to be 11111111 00000000 + 1 Cin S 00000000 Cout = 1 B set to 11111111 Cin then set to 1 Time from when Cin at 50% until Cout a 50% –1.035ns(!!!)

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Zhuang Full Adder Same test case as before Delay found to be.662ns Significanly faster than other static CMOS implementation

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Zhuang Full Adder Simulated with parasitics added Same test pattern applied Delay now found to be.970ns Still faster than other adder without parasitics Use Zhuang full adder

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Zhuang Full Adder Layout Had Zhuang layout from before Fit nicely in bitslice in IP library –80λ width –Exports at correct places –Perfect! Zhuang Full Adder layout completed

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Zhuang Full Adder Simulation Exported layout to SPICE Same test case as used before Delay is now 1.23ns Completed ALU ready to be placed in bitslice ~550 λ

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Adders Wrap Up Total bitslice size ~2500λ Well under 3500λ Distorted (squished horizontally, too long to display) view of completed bitslice.

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Adder Wrap Up Not fast enough though –Dynamic CMOS? –Static carry lookahead use more space?

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