Presentation on theme: "Chien M. Ta Chee Hong Yong Wooi Gan Yeoh A 2.7mW linear-in-dB VGA with 60dB tuning range and two DC offset cancellation loops Radio-Frequency Integration."— Presentation transcript:
Chien M. Ta Chee Hong Yong Wooi Gan Yeoh A 2.7mW linear-in-dB VGA with 60dB tuning range and two DC offset cancellation loops Radio-Frequency Integration Technology – RFIT 2005 Nov. 30 – Dec. 2, 2005 Institute of Microelectronics
Page 2 Outline Introduction Specifications Circuit description Measurement results Concluding remarks and future works Acknowledgement
Page 3 Introduction Motivation A Direct Conversion Receiver for Ultra-Wideband communications Objective A low-power Variable Gain Amplifier with DC Offset Cancellation mechanism
Page 4 Specifications SpecificationValueCondition Technology0.18-μm bulk CMOS Power supply1.8V Bandwidth> 100MHz@ all gain levels Low cutoff frequency< 500kHz Output swing1 V Peak-to-peak differentially DC offset cancellationOutput DC offset <5mV @60dB gain, 10mV input offset Power consumptionAs low as possible
Page 5 Architecture LPF + _ Fixed-gain Variable-gain LPF + _ V-to-I converter IN OUT Control voltage Variable-gain Adder Two DC offset cancellation loops at the input and the output of the VGA to suppress DC offset in the input signal and DC offset caused by mismatches in the circuit itself.
Page 6 DC offset cancellation LPF + _ Fixed-gain Adder Output DC offset is extracted and negatively fed back to cancel the DC offset at the input of the fixed gain block.
Page 7 Fixed-gain stage IN 1 IN 2 OUT 1 OUT 2 IsIs IsIs Differential pair with degenerative resistor: simple, stable, and linear Split tail current: save voltage headroom Issues: matching between the components (solved by interdigitizing)
Page 8 Variable-gain stage IN 1 OUT 1 OUT 2 I s1 I s2 IN 2 Gilbert cell with degenerative resistors: large gain range (30dB linear-in-dB gain range) Split tail current: save voltage headroom Issues: matching between the components (solved by interdigitizing) VcVc I s2 I s1 V-to-I converter
Page 9 Gain tuning curve Gain can be tuned linear-in-dB from -3dB to 57dB (the specification is from 0dB to 60dB) when the control voltage is varied from 0.2V to 0.9V
Page 10 Frequency response Low cutoff frequency at 600kHz (specification is <500kHz) 3-dB bandwidth of 130MHz (specification is >100MHz)
Page 11 DC offset cancellation Output DC offset is below 20mV for input DC offset up to 40mV and below 10mV for input DC offset up to 10mV
Page 12 Summary of the design ConditionSpecificationMeasurement Technology0.18-μm bulk CMOS Power supply1.8V Power consumption2.7mW Gain0dB to 60dB-3dB to 57dB Bandwidth> 100MHz130MHz Low cutoff frequency< 500kHz500kHz – 600kHz Output swing Peak-to-peak differentially 1V Offset cancellation @60dB gain, 10mV input offset <5mV<10mV IIP3-29dBm
Page 13 Concluding remarks and Future works What have been achieved? A functional VGA architecture with two DC offset cancellation loops Tunable gain in dB-linear fashion with respect to the control voltage Maximum gain is as high as 57dB Satisfactory bandwidth of 130MHz Very low power consumption, 2.7mW Very small die area, 243μm x 264μm (0.064mm 2 ) What to do next? Improve the linearity by redesigning the last stage of the VGA; more power consumption is needed Improve noise performance of the VGA by carefully redesigning the first stage Reduce mismatch in the layout to get better DC offset cancellation
Page 14 Acknowledgement Dr. Lin Fujiang for coordinating the project Dr. Zheng Yuanjin, Mr. Ben Choi, Mr. Teo Tee Hui, and Mr. Wong Sheng Jau for their advice during the design Ms. Wu Ye and Mr. Ram Chandra Yadav for reviewing the paper IME management
Page 16 Benchmarking ReferenceTechnolog y SupplyCurrentPowerAreaBWGainLinearityNoise FigureYear Hung Yan Cheung et al. CMOS 0.35um 3V7mW (AGC) 20MHz-30dB to 50dB THD = 40dBc2001 S. Otaka et al.BiCMOS f T = 20GHz 3V36mW (w/Buffer) 1mm 2 50MHz to 500MHz -35dB to 43dB -38dBm @ 43dB -8dBm @ -35dB <5dB2000 T. Yamaji et al.CMOS 0.25um 2.5V11mA30MHz to 210MHz -35dB to 55dB P1dB=-40dBm @ 55dB P1dB=-8dBm @ -35dB IIP3=-28dBm @ 55dB IIP3=7dBm @ -35dB 8dB @ max gain 2002 J. J. F. RijnsCMOS 0.8um 5V5mA0.175mm 2 15MHz (Cload = 7pF) THD -60dB 1996 G. S. Sahota and C. J. Persico BiCMOS3.6V12mA43.2mW300MHz-45dB to 45dB 1997 W. C. Song et al.CMOS 0.35um 3V10.8mA32.4mW580um x 660um 200MHz-50dB to 50dB 10dBm @ -50dB -30dBm @ 50dB 2000 This workCMOS 0.18um 1.8V1.5mA2.7mW (excluding buffer) 243μm x 264μm 130MHz-3dB to 57dB -49dBm @ 57dB -29dBm @ 7dB 2005
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