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V6 GTX Gu Yongguo Note: this draft has HXT and Fujisan content removed because it will be given to reps and external-to-xilinx. To engage customers on.

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Presentation on theme: "V6 GTX Gu Yongguo Note: this draft has HXT and Fujisan content removed because it will be given to reps and external-to-xilinx. To engage customers on."— Presentation transcript:

1 V6 GTX Gu Yongguo Note: this draft has HXT and Fujisan content removed because it will be given to reps and external-to-xilinx. To engage customers on this material, please contact Panch Chandrasekaran or Anthony Torza.

2 Agenda Transceiver Overview Virtex-6 GTX Overview
Transceiver Roadmap Virtex-6 GTX Table Virtex-6 GTX Overview Die Allocation PLL Clock resources Virtex-6 GTX Architecture Transmitter Receiver DRP Virtex-6 GTX PCB

3 Transceiver Overview Next-Generation Serial Connectivity Roadmap
I/O Speed 11.2 Gbps GTH Features: Highest Serial BW Advanced RX EQ 10 Gbps 9.95 Gbps 6.5 Gbps GTX Advanced Rx EQ Low latency Low Power PCI Express IP GTX Advanced Rx EQ Low latency Low Power PCI-Express PHY PCI Express IP Easy to Use 5 Gbps 3.125 Gbps GTP Low Power PCI-Express PHY PCI Express IP Easy to Use GTP Lowest Cost Low Power PCI-Express PHY PCI-Express IP Easy to Use 2.488 Gbps 614 Mbps 150 Mbps 3

4 Virtex-6 LXT & SXT 16 of 18 device-package combinations have transceivers

5 Agenda Transceiver Overview Virtex-6 GTX Overview
Transceiver Roadmap Virtex-6 GTX Table Virtex-6 GTX Overview Die Allocation Reference Clock PLL Virtex-6 GTX Architecture Transmitter Receiver DRP Virtex-6 GTX PCB

6 GTX Allocation

7 Transceiver Overview Virtex-6 Transceivers - GTX
Available in Virtex-6 LXT, SXT and HXT Range: 480 Mbps – 6.5 Gbps Compliant to major protocol standards Gigabit Ethernet, PCI Express Gen1 & Gen2, OC-48, XAUI, HD-SDI, OBSAI, CPRI, SRIO, FC-1/2/4, Interlaken, CEI-6 OOB signaling for PCI Express Built-in Linear EQ, DFE and Tx Pre-emphasis Highly flexible clocking Independent PLLs for TX and RX Power dissipation: < 150 mW typ

8 Reference Clock Easier than it looks
Intelligent Pin Selection Connect IBUFDS_E1 to MGTREFCLKTX/RX[0] Wizard will sort this out for you! The wizard selections will make the correct connections Includes north and south bound routes Advanced Users: Can use MUX connections to specify specific clock routes Complex view available to assist in Clock Switching applications 2 Refclks (RefClk0 and 1) from pins (Like Virtex-5) 2 Refclks cascade from North Quad PERFCLK and GREFCLK From Fabric 2 Refclks cascade from South Quad

9 GTX Reference Clock Conceptual View

10 GTX Transceiver Detailed Diagram

11 Clock Generation Comparison:
Virtex 5 GTP/GTX Clocking: Virtex 6 Clocking:

12 Reference clock connection Single GTX w/ Single Refclk

13 Reference clock connection Multiple GTXs w/ Multiple Refclks

14 Reference clock connection Single Clock Sharing
Note Each external RefClk can feed up to 3 Quads (12 transceivers) MGTRefclk directly from an external pin via IBUFDS Quad (n+1) Quad (n) MGTRefClk comes from local pins Quad (n-1)

15 PLL Architecture

16 PLL Selection: Typical Case
Upstream and downstream are same rate XAUI PCIe Aurora Most other protocols… Power down TX PLL = Power Savings

17 PLL Selection: Fancy Case
Upstream and downstream are different rates! HD-SDI Transponder w/ FEC and w/o FEC rates Additional Flexibility

18 This output used by both TX and RX
GTX Recall MGTRefClk is local, so we select MGTREFCLKRX[0] For Aurora, we use the same RefClk for TX and RX directions TX PLL is powered down to save power Remember… This output used by both TX and RX MGTRefClk from local pins

19 Agenda Transceiver Overview Virtex-6 GTX Overview
Transceiver Roadmap Virtex-6 GTX Table Virtex-6 GTX Overview Die Allocation Reference Clock PLL Virtex-6 GTX Architecture Transmitter Receiver DRP Virtex-6 GTX PCB

20 Overview

21 Transmitter Diagram

22 Data Width

23 TXUSRCLK/TXUSRCLK2

24 TXUSRCLK INTERNAL GENERATION
TXUSRCLK tied to GND TXUSRCLK is derived from TXUSRCLK2 TXUSRCLK is not faster than TXUSRCLK2 Internal divider only

25 Clock scheme Example 2-Byte interface
TXUSRCLK is generated internally 1 BUFG is saved Internal and internal data widths are equal

26 Clock scheme Example 4-Byte interface
WINT = WEXT FTXUSRCLK2 = FTXUSRCLK / 2 TXUSRCLK is generated externally by MMCM

27 Clock scheme Example 1-Byte interface
FTXUSRCLK2 = FTXUSRCLK * 2 TXUSRCLK is generated internally 1 BUFG is saved

28 Clock scheme Example Multi-lanes with 2-Byte interface
Clock is same to single 2-byte application But share among other lanes Similar case to other interfaces

29 Transmitter Resets

30 Transmitter Reset Coverage

31 Reset Recommendation After Power-up and Configuration
The entire GTX TX is reset automatically after configuration-provided TXPLLPOWERDOWN is Low. The supplies for the calibration resistor and calibration resistor reference must be powered up before configuration to ensure correct calibration of the termination impedance of all transceivers. After Turning on a Reference Clock to the TX PLL The reference clock source(s) and the power to the GTX transceiver(s) must be available before configuring the FPGA. The reference clock must be stable before configuration especially when using PLL-based clock sources (e.g., voltage controlled crystal oscillators). If the reference clock(s) changes or GTX transceiver(s) are powered up after configuration, GTXTXRESET is asserted to allow the TX PLL(s) to lock. After Changing the Reference Clock to the TX PLL Whenever the reference clock input to the TX PLL is changed, the TX PLL must be reset afterwards to ensure that it locks to the new frequency. The GTXTXRESET port must be used for this purpose. Refer to “Reference Clock Selection,” page 55 for more details. After Assertion/Deassertion of TXPOWERDOWN After the TXPOWERDOWN signal is deasserted, GTXTXRESET must be asserted. TX Rate Change with the TX Buffer Enabled After TXRATEDONE is asserted, indicating the rate change has completed, the TX PLL output clock dividers must be reset followed by a TX PCS reset. To reset the clock dividers, GTXTEST[1] is asserted for at least 16 TXUSRCLK2 cycles. To reset the TX PCS, TXRESET is asserted. To automatically reset the TX buffer after the rate change, the TX_EN_RATE_RESET_BUF attribute is set to “TRUE.” TX Rate Change with the TX Buffer Bypassed output clock dividers must be reset. Phase alignment must be performed again followed by reset of the TX PCS. See “TX Buffer Bypass,” page 104 for details on the rate change procedure. TX Parallel Clock Source Reset The clocks driving TXUSRCLK and TXUSRCLK2 must be stable for correct operation. These clocks are often driven from an MMCM in the FPGA to meet phase and frequency requirements. If the MMCM loses lock and begins producing incorrect output, TXRESET must be used to hold TX PCS in reset until the clock source is locked again. If the TX buffer is bypassed and phase alignment is in use, phase alignment must be performed again after the clock source relocks.

32 TXBUFFER Remove phase difference between TXUSRCLK and XCLK
Can be bypassed for low latency application Advanced and some complex

33 Buffer Bypass Steps Set the following attributes with their values as follows: Set TXOUTCLK_CTRL to use either TXPLLREFCLK_DIV2 or TXPLLREFCLK_DIV1 Set TX_XCLK_SEL to TXUSR Set TX_BUFFER_USE to FALSE Set TX_PMADATA_OPT to TRUE After power-on, make sure TXPMASETPHASE and TXENPMAPHASEALIGN are driven Low. Make sure that the input port TXDLYALIGNDISABLE is driven High. Apply GTXTXRESET and wait for TXRESETDONE to go High. Wait for all clocks to stabilize, then assert TXDLYALIGNRESET for at least 16 TXUSRCLK2 clock cycles. Drive TXENPMAPHASEALIGN High. Keep TXENPMAPHASEALIGN High unless the phase-alignment procedure must be repeated. Driving TXENPMAPHASEALIGN Low causes phase alignment to be lost. Wait 32 TXUSRCLK2 clock cycles and then drive TXPMASETPHASE High. Wait the number of required TXUSRCLK2 clock cycles as specified in Table 3-20, and then drive TXPMASETPHASE Low. The phase of the PMACLK is now aligned with TXUSRCLK. Drive TXDLYALIGNDISABLE Low. Optional: Keep TXDLYALIGNDISABLE High to disable the TX delay aligner.

34 Phase Alignment after GTXTXRESET

35 Phase Re-alignment conditions
GTXTXRESET is asserted TXPLLPOWERDOWN is deasserted The clocking source changed The line rate of the GTX TX transceiver changed

36 Phase Alignment after Line Rate changing
1. In non PCI Express mode, a TX rate change completion occurs when a TXRATEDONE pulse is detected. In PCI Express mode, a TX rate change completion occurs when a PHYSTATUS pulse is detected following a TXRATEDONE pulse. 2. When a rate change completion is detected, assert TXDLYALIGNDISABLE. 3. Assert GTXTEST[1] for at least 16 TXUSRCLK2 cycles to reset the TX PLL output clock divider. Assert TXDLYALIGNRESET for at least 16 TXUSRCLK2 cycles to reset the TX delay aligner. 5. Hold TXENPMAPHASEALIGN asserted. 6. Wait for at least 32 TXUSRCLK2 cycles. 7. Assert TXPMASETPHASE for the required TXUSRCLK2 cycles specified in Table 3-20. 8. Deassert TXDLYALIGNDISABLE. (Optional: Hold TXDLYALIGNDISABLE asserted to disable the TX delay aligner.) 9. Assert the TXRESET pulse and wait for TXRESETDONE to be asserted. 10. For PCI Express mode, the “USER_PHYSTATUS” user signal must be generated and used as PIPE PHYSTATUS. Under normal operation, USER_PHYSTATUS follows the GTX PHYSTATUS signal. During rate change and subsequent TX phase alignment, USER_PHYSTATUS must gate the GTX PHYSTATUS and delay its assertion until after the TX phase alignment sequence is completed.

37 TX Parallel Clock Divider

38 TX Driver

39 TXDIFFCTRL

40 TXPOSTEMPHASIS Control the Post-Cursor Preemphasis

41 TXPREEMPHASIS Control the Pre-Cursor Preemphasis

42 Receiver Diagram

43 RX AFE

44 RX Linear Equalization

45 RXEQMIX Setting Determine the operating data rate.
Determine the channel loss (board) in dB at data rate/2. This is the differential insertion loss from measured or extracted S-parameter data commonly referred to as Sdd21. Pick the appropriate RXEQMIX setting from the relative gain plot. Always make sure that the transmit amplitude is sufficient when picking modes with a higher gain because there is DC attenuation of the signal. Reference the absolute gain plot. Based on these results, the appropriate setting of RXEQMIX can be picked.

46 DFE

47 RX CDR Edge Sampler Data Sampler Scan Sampler Detect the Eye edge
Real Data Sampling Point Scan Sampler For Margin

48 CDR Lock Detection Finding known data in the incoming data stream (for example, commas or A1/A2 framing characters). Several consecutive known data patterns must be received without error to indicate a CDR lock. Using the LOS state machine Incoming data is 8B/10B encoded If CDR is locked, the LOS state machine moves to the SYNC_ACQUIRED state and stays there.

49 RX parallel clock divider

50 RX Margin Scan Attributes

51 Eye Margin related to bit error

52 Eye Margin Operating Steps
Set proper RXREQMIX Improper RXREQMIX can lead to incorrect DFE operating Run DFE with Auto-Calibration To get the max eye height With NO bit error Run manual DFE with proper DFE setting Copy TAP monitors to TAP set ports Assert DFETAPOVRD Set RX_EYE_SCANMODE to 2’b01 Via DRP Modify RX_EYE_OFFSET to control scan sampling point Judge by DFEEYEDACMONITOR[4:0] 5’b11111 for 200mV Minimum input is 120mV (about 5’b10011)

53 RX Buffer Bypass

54 RX Phase Alignment steps
Set the following attributes with their values as follows: Set RXRECCLK_CTRL: 2 byte or 4 byte – use RXRECCLKPMA_DIV2 1 byte – use RXRECCLKPMA_DIV1 Set RX_BUFFER_USE to FALSE to bypass the RX elastic buffer. Set RX_XCLK_SEL to RXUSR. Make sure all the input ports RXENPMAPHASEALIGN and RXPMASETPHASE are driven Low Make sure that the input port RXDLYALIGNDISABLE is driven High. Reset the RX datapath using GTXRXRESET or the RXCDRRESET. If an MMCM is used to generate RXUSRCLK/RXUSRCLK2 clocks, wait for the MMCM to lock. Wait for the CDR to lock and provide a stable RXRECCLK. Assert RXDLYALIGNRESET for 20 RXUSRCLK2 clock cycles. Drive RXENPMAPHASEALIGN High Keep RXENPMAPHASEALIGN High unless the phase-alignment procedure must be repeated. Driving RXENPMAPHASEALIGN Low causes phase align to be lost Wait 32 RXRUSCLK2 clock cycles and then drive RXPMASETPHASE High for 32 RXUSRCLK2 cycles and then deassert it. Drive RXDLYALIGNDISABLE Low.

55 Timing waveform

56 Agenda Transceiver Overview Virtex-6 GTX Overview
Transceiver Roadmap Virtex-6 GTX Table Virtex-6 GTX Overview Die Allocation PLL Clock resources Virtex-6 GTX Architecture Transmitter Receiver DRP Virtex-6 GTX PCB

57 Power supplier Power can be shared between Quads

58 RCAL Resistor PCB Layout

59 Power Supplying All column is in used
FF484/FF784 has only ONE MGTAVCCINT plane FF1156/FF1759 has TWO MGTAVCCINT planes: South and North

60 Power Supplying MGTAVCC plane

61 Power Supplying No MGT used in Column

62 Power Supplying Partially used Column --- Whole Quad unused

63 Power Supplying Partial Quad unused

64 Quad used Priority FF484/FF784
Priority 1: MGT115 This Quad should be used if any of the GTX transceivers in the device are used in the application. It contains the RCAL circuit that is required for the RX and TX internal termination resistors. Priority 2: MGT114/116 Depending on availability in the package, these Quads have equal priority.

65 Quad used Priority FF1156/FF1759
Priority 1: MGT115 This Quad should be used if any of the GTX transceivers in the device are used in the application. It contains the RCAL circuit that is required for the RX and TX internal termination resistors. Priority 2: MGT116/117/118 If present in the Virtex-6 device, these Quads are connected in the package to the same power planes as MGT115, the north power plane group. Therefore they have equal priority. Because the north power planes need to be powered for MGT115, these Quads are also powered; therefore they can be used without additional power supply connections. Priority 3: MGT110/111/112/113/114 These transceivers are connected to the south power planes. They should be used if all Quads on the north power planes have already been utilized. If any of these Quads are used, then all MGTAVCC_N and MGTAVTT_S pins need to be connected to the appropriate power supply voltage.

66 Reference Clock Interface LVDS Clock

67 Reference Clock LVPECL Clock


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