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Intellectual Property (IP) Cores By Jannin Joy A. Ramirez.

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Presentation on theme: "Intellectual Property (IP) Cores By Jannin Joy A. Ramirez."— Presentation transcript:

1 Intellectual Property (IP) Cores By Jannin Joy A. Ramirez

2 Semiconductor industry: Then and Now THEN SC companies provided product definition design manufacturing assembly customer support Goal: system integration NOW chipless companies only provide design information e.g. ARM – microprocessors, peripherals, and chips Amphion – digital video and broadband wireless applications

3 IP Core: What is it exactly? A design function with well-defined interfaces. a design block for a specific chip that handles a well-defined piece of functionality A block of logic or data that can be used in making application-specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs) e.g. CPUs, Ethernet controllers, UARTs Ethernet – LAN technology, IOBASE-T Universal Asynchronous Receiver/Transmitter – microchip w/ programming that controls PCs interface to attached serial devices

4 IP core Design flow ©Whitney and Neville-Neil

5 How are IP cores created? Register Transfer Language (RTL) – a hardware programming language Synthesis programs – read RTL and translate them directly to circuits that are implemented on the silicon Simulation programs – read RTL and let designers exercise functionality and check its correctness

6 EDA (electronic design automation) Tools DESIGN STAGETOOLS SUPPORTED RTL Simulation And Gate Level Simulation Synopsys Chronologic VCS v5.0.1A – Unix Cadence Verilog XL v2.6.37 Unix ModelTech ModelSim v5.3d WinNT Logic SynthesisSynopsys Design Compiler v99.10-4 Test SynthesisSynopsys Test Compiler v99.10-4

7 IP core categories SOFT IP – core is not mapped onto silicon (+) portable across technology generations (-) raw RTL code must be tailored to a target technology through logic design process HARD IP – physical manifestations of the IP design (+) best for plug-and-play applications (-) less portable and flexible FIRM IP – combination of best attributes of both soft and hard (+) portability and silicon optimization

8 Comparison of Attributes of IP formats SOFT IPFIRM IPHARD IP Delivery format RTL codeTechnology specific netlist GDSII data Portability/ Reusability HIGH LOW Silicon Optimization LOWHIGHHIGHEST Integration effort required HIGH Logic design process required LOW Place and rout tools LOW Drop into SoC design

9 ARM CPU cores ARM CPU cores cover a wide range of performance and features enabling system designers to create solutions that meet their precise requirements. Three system categories: Embedded real-time – storage, automotive, industrial and networking applications Open platforms – devices running platform OS like Linus, PalmOS, Windows CE Secure applications – SIM cards and payment terminals

10 Cache Size (Inst/Data) Tightly Coupled Memory Memory management AHB Bus Interface Clock MHz EMBEDDED CORES ARM7TDMI No Yes133 ARM7TDMI-S No Yes100-133 ARM1026EJ-S VariableYesMMU+MPUDual AHB266-325 PLATFORM CORES ARM720T 8K unifiedNoMMUYes100 ARM1136J(F)-S VariableYesMMUQuad 64- bit AHB 333-400

11 Latest version of ARM CPU cores ARM v6 Architecture KEY AREAS: Memory Management average fetch and data latency is reduced more efficient bus usage; less bus activity yields significant power savings as a result of reduced memory access

12 Multiprocessing Multiprocessor systems share data efficiently by sharing memory ARM v6 data sharing and synchronization capabilities make it easier to implement multiprocessor systems

13 Multimedia Support Single Instruction Multiple Data (SIMD) capabilities enable more efficient software implementation of media applications such as audio and video encoders

14 Data Handling Endianism refers to the way data is referenced and stored in memory SoC integration: little endian OS environment and interfaces (USB,PCI) with big endian data (TCP/IP packet, MPEG stream) ARM v6 handles data in mixed-endian systems

15 Latest version of ARM CPU core Benefits of ARM v6 Architecture 30 percent increase in system performance * level-one memory system, which includes features such as a tightly-coupled Direct Memory Access (DMA) controller and re-architected cache, Up to 8x performance increase for media applications * SIMD capabilities boost the performance of media applications such as audio and video encoder/decoders by up to four times, * also includes enhanced instruction set support for motion estimation.

16 ARM11 Family: ARM1136J-S and ARM 1136J(F)-S Low power consumption o < 0.4mW/MHz (0.13µm, 1V) including cache controllers o Energy saving power-down modes address static leakage currents in advanced processes High performance integer processor o 8-stage integer pipeline delivers high clock frequency o Separate load-store and arithmetic pipelines Branch Prediction and Return Stack High performance memory system design o Supports 4-64k cache sizes o Optional tightly coupled memories with DMA for multi-media applications o High-performance 64-bit memory system speeds data access for media processing and networking applications o ARMv6 memory system architecture accelerates OS context-switch

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