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Chapter 5:

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1 / 60 Sequential Circuits Combinational Circuit Memory Elements Inputs Outputs Asynchronous Synchronous Combinational Circuit Flip-flops Inputs Outputs Clock

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2 / 60 Latches SR Latch S R Q 0 QQ’ Q = Q 0 Initial Value

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3 / 60 Latches SR Latch S R Q 0 Q Q’ Q = Q 0

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4 / 60 Latches SR Latch S R Q 0 Q Q’ Q = 0 Q = Q 0

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5 / 60 Latches SR Latch S R Q 0 Q Q’ Q = 0 Q = Q 0 Q = 0

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6 / 60 Latches SR Latch S R Q 0 Q Q’ Q = 0 Q = Q 0 Q = 1

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7 / 60 Latches SR Latch S R Q 0 Q Q’ Q = 0 Q = Q 0 Q = 1

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8 / 60 Latches SR Latch S R Q 0 Q Q’ Q = 0 Q = Q 0 Q = 1 Q = Q’ 0

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9 / 60 Latches SR Latch S R Q 0 Q Q’ Q = 0 Q = Q 0 Q = 1 Q = Q’ 0

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10 / 60 Latches SR Latch S RQ 0 Q0Q Q=Q’=0 No change Reset Set Invalid S R Q 0 Q=Q’= Q0Q0 Invalid Set Reset No change

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11 / 60 Latches SR Latch S RQ 0 Q0Q Q=Q’=0 No change Reset Set Invalid S’ R’Q 0 Q=Q’= Q0Q0 Invalid Set Reset No change

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12 / 60 Controlled Latches SR Latch with Control Input C S RQ 0 x x Q0Q Q0Q Q=Q’Q=Q’ No change Reset Set Invalid

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13 / 60 Controlled Latches D Latch (D = Data) C DQ 0 x Q0Q No change Reset Set C Timing Diagram D Q t Output may change

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14 / 60 Controlled Latches D Latch (D = Data) C DQ 0 x Q0Q No change Reset Set C Timing Diagram D Q Output may change

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15 / 60 Flip-Flops Controlled latches are level-triggered Flip-Flops are edge-triggered C CLKPositive Edge CLKNegative Edge

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16 / 60 Flip-Flops Master-Slave D Flip-Flop D Latch (Master) DCDC Q D Latch (Slave) DCDC QQD CLK D Q Master Q Slave Looks like it is negative edge-triggered MasterSlave

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17 / 60 Flip-Flops Edge-Triggered D Flip-Flop DQ Q DQ Q Positive Edge Negative Edge

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18 / 60 Flip-Flops JK Flip-Flop JQ QK D = JQ’ + K’Q

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19 / 60 Flip-Flops T Flip-Flop D = TQ’ + T’Q = T Q JQ Q K T DQ Q T D = JQ’ + K’Q TQ Q

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20 / 60 Flip-Flop Characteristic Tables DQ Q DQ(t+1) Reset Set JKQ(t+1) 00Q(t)Q(t) Q’(t) No change Reset Set Toggle JQ QK TQ Q TQ(t+1) 0Q(t)Q(t) 1Q’(t) No change Toggle

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21 / 60 Flip-Flop Characteristic Equations DQ Q DQ(t+1) Q(t+1) = D JKQ(t+1) 00Q(t)Q(t) Q’(t) Q(t+1) = JQ’ + K’Q JQ QK TQ Q TQ(t+1) 0Q(t)Q(t) 1Q’(t) Q(t+1) = T Q

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22 / 60 Flip-Flop Characteristic Equations Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) No change Reset Set Toggle

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23 / 60 Flip-Flop Characteristic Equations Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) No change Reset Set Toggle

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24 / 60 Flip-Flop Characteristic Equations Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) No change Reset Set Toggle

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25 / 60 Flip-Flop Characteristic Equations Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) No change Reset Set Toggle

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26 / 60 Flip-Flop Characteristic Equations Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) K 0100 J1101 Q Q(t+1) = JQ’ + K’Q

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27 / 60 Flip-Flops with Direct Inputs Asynchronous Reset DQ Q R Reset R’DCLKQ(t+1) 0xx0

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28 / 60 Flip-Flops with Direct Inputs Asynchronous Reset DQ Q R Reset R’DCLKQ(t+1) 0xx0 10 ↑ 0 11 ↑ 1

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29 / 60 Flip-Flops with Direct Inputs Asynchronous Preset and Clear PR’CLR’DCLKQ(t+1) 10xx0 DQ Q CLR Reset PR Preset

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30 / 60 Flip-Flops with Direct Inputs Asynchronous Preset and Clear PR’CLR’DCLKQ(t+1) 10xx0 01x x 1 DQ Q CLR Reset PR Preset

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31 / 60 Flip-Flops with Direct Inputs Asynchronous Preset and Clear PR’CLR’DCLKQ(t+1) 10xx0 01x x ↑ ↑ 1 DQ Q CLR Reset PR Preset

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32 / 60 Analysis of Clocked Sequential Circuits The State ●State = Values of all Flip-Flops Example A B = 0 0

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33 / 60 Analysis of Clocked Sequential Circuits State Equations A(t+1) = D A = A(t) x(t)+B(t) x(t) = A x + B x B(t+1) = D B = A’(t) x(t) = A’ x y(t) = [A(t)+ B(t)] x’(t) = (A + B) x’

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34 / 60 Analysis of Clocked Sequential Circuits State Table (Transition Table) A(t+1) = A x + B x B(t+1) = A’ x y(t) = (A + B) x’ Present State Input Next State Output ABxABy t+1 t t

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35 / 60 Analysis of Clocked Sequential Circuits State Table (Transition Table) A(t+1) = A x + B x B(t+1) = A’ x y(t) = (A + B) x’ Present State Next StateOutput x = 0x = 1x = 0x = 1 ABABAB yy t+1 t t

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36 / 60 Analysis of Clocked Sequential Circuits State Diagram /00/0 0/10/1 1/01/0 1/01/0 1/01/0 1/01/00/10/1 0/10/1 AB input/output Present State Next StateOutput x = 0x = 1x = 0x = 1 ABABAB yy

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37 / 60 Analysis of Clocked Sequential Circuits D Flip-Flops Example: DQ Q x CLK y A Present State Input Next State A xy A ,11 01,10 A(t+1) = D A = A x y

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38 / 60 Analysis of Clocked Sequential Circuits JK Flip-Flops Example: J A = BK A = B x’ J B = x’K B = A x A(t+1) = J A Q’ A + K’ A Q A = A’B + AB’ + Ax B(t+1) = J B Q’ B + K’ B Q B = B’x’ + ABx + A’Bx’ Present State I/P Next State Flip-Flop Inputs ABxABJAJA KAKA JBJB KBKB

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39 / 60 Analysis of Clocked Sequential Circuits JK Flip-Flops Example: Present State I/P Next State Flip-Flop Inputs ABxABJAJA KAKA JBJB KBKB

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40 / 60 Analysis of Clocked Sequential Circuits T Flip-Flops Example: T A = B xT B = x y = A B A(t+1) = T A Q’ A + T’ A Q A = AB’ + Ax’ + A’Bx B(t+1) = T B Q’ B + T’ B Q B = x B Present State I/P Next State F.F Inputs O/P ABxABTATA TBTB y

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41 / 60 Analysis of Clocked Sequential Circuits T Flip-Flops Example: Present State I/P Next State F.F Inputs O/P ABxABTATA TBTB y /00/0 1/01/0 0/00/0 1/01/0 1/01/0 1/11/1 0/00/0 0/10/1

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42 / 60 Mealy and Moore Models Present State I/P Next State O/P ABxABy Mealy state outputinput For the same state, the output changes with the input Present State I/P Next State O/P ABxABy Moore state outputinput For the same state, the output does not change with the input

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43 / 60 Moore State Diagram State / Output 0 0 / 00 1 / / 11 0 /

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44 / 60 Timing Diagram 0 0 / 00 1 / / 11 0 / CLK State A B y x No effect A B xy

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45 / 60 Timing Diagram /0 1/0 1/1 0/0 1/1 1/0 CLK State A B y x 1010 A B xy

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46 / 60 Design of Clocked Sequential Circuits Example: Detect 3 or more consecutive 1’s S0 / 0S0 / 0S 1 / 0 S 3 / 1S 2 / StateA B S0S0 0 S1S1 0 1 S2S2 1 0 S3S3 1

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47 / 60 Design of Clocked Sequential Circuits Example: Detect 3 or more consecutive 1’s Present State Input Next State Output ABxABy S0 / 0S0 / 0S 1 / 0 S 3 / 1S 2 /

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48 / 60 Design of Clocked Sequential Circuits Example: Detect 3 or more consecutive 1’s Present State Input Next State Output ABxABy A(t+1) = D A (A, B, x) = ∑ (3, 5, 7) B(t+1) = D B (A, B, x) = ∑ (1, 5, 7) y (A, B, x) = ∑ (6, 7) D Synthesis using D Flip-Flops

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49 / 60 Design of Clocked Sequential Circuits with D F.F. Example: Detect 3 or more consecutive 1’s D A (A, B, x) = ∑ (3, 5, 7) = A x + B x D B (A, B, x) = ∑ (1, 5, 7) = A x + B’ x y (A, B, x) = ∑ (6, 7) = A B D Synthesis using D Flip-Flops B 0010 A0110 x B 0100 A0110 x B 0000 A0011 x

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50 / 60 Design of Clocked Sequential Circuits with D F.F. Example: Detect 3 or more consecutive 1’s D A = A x + B x D B = A x + B’ x y = A B D Synthesis using D Flip-Flops

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51 / 60 Flip-Flop Excitation Tables Present State Next State F.F. Input Q(t)Q(t)Q(t+1)D Present State Next State F.F. Input Q(t)Q(t)Q(t+1)JK (No change) 0 1 (Reset) 0 x 1 x x 1 x (Set) 1 1 (Toggle) 0 1 (Reset) 1 1 (Toggle) 0 0 (No change) 1 0 (Set) Q(t)Q(t)Q(t+1)T

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52 / 60 Design of Clocked Sequential Circuits with JK F.F. Example: Detect 3 or more consecutive 1’s Present State Input Next State Flip-Flop Inputs ABxAB JAJA KAKA JBJB KBKB x 1 x x 1 x 0 x 1 x 0 J A (A, B, x) = ∑ (3) d JA (A, B, x) = ∑ (4,5,6,7) K A (A, B, x) = ∑ (4, 6) d KA (A, B, x) = ∑ (0,1,2,3) J B (A, B, x) = ∑ (1, 5) d JB (A, B, x) = ∑ (2,3,6,7) K B (A, B, x) = ∑ (2, 3, 6) d KB (A, B, x) = ∑ (0,1,4,5) JK Synthesis using JK F.F. 0 x 1 x x 1 0 x 1 x x 1 x 0

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53 / 60 Design of Clocked Sequential Circuits with JK F.F. Example: Detect 3 or more consecutive 1’s J A = B xK A = x’ J B = xK B = A’ + x’ JK Synthesis using JK Flip-Flops B 0010 Axxxx x B xxxx A1001 x B 01xx A01xx x B xx11 Axx01 x

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54 / 60 Design of Clocked Sequential Circuits with T F.F. Example: Detect 3 or more consecutive 1’s Present State Input Next State F.F. Input ABxABT A T B T Synthesis using T Flip-Flops T A (A, B, x) = ∑ (3, 4, 6) T B (A, B, x) = ∑ (1, 2, 3, 5, 6)

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55 / 60 Design of Clocked Sequential Circuits with T F.F. Example: Detect 3 or more consecutive 1’s T A = A x’ + A’ B x T B = A’ B + B x T Synthesis using T Flip-Flops B 0010 A1001 x B 0111 A0101 x

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56 / 60 Homework Mano ●Chapter 5 ♦ 5-1 ♦ 5-3 ♦ 5-6 ♦ 5-8 ♦ 5-9

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57 / 60 Homework 5-1The D latch is constructed with four NAND gates and an inverter. Consider the following three other ways for obtaining a D latch. In each case, draw the logic diagram and verify the circuit operation. (a) Use NOR gates for the SR latch part and AND gates for the other two. An inverter may be needed. (b) Use NOR gates for all four gates. Inverters may be needed. (c) Use four NAND gates only (without an inverter). This can be done by connecting the output of the upper gate that goes to the SR latch to the input of the lower gate instead of the inverter output.

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58 / 60 Homework 5-3Show that the characteristic equation for the complement output of a JK flip-flop is Q’(t+1) = J’Q + K Q 5-6A sequential circuit with two D flip-flops, A and B; two inputs, x and y; and one output, z, is specified by the following next-state and output equations: A(t+1) = x’ y + x A B(t+1) = x’ B + x A z = B (a) Draw the logic diagram of the circuit. (b) List the state table for the sequential circuit. (c) Draw the corresponding state diagram.

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59 / 60 Homework 5-8Derive the state table and the state diagram of the sequential shown circuit. Explain the function that the circuit performs.

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60 / 60 Homework 5-9A sequential circuit has two JK flip-flops A and B and one input x. The circuit is described by the following flip-flop input equations: J A = x K A = B’ J B = x K B = A (a) Derive the state equations A(t+1) and B(t+1) by substituting the input equations for the J and K variables. (b) Draw the state diagram of the circuit.

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