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IO - 1Embedded Systems Lab./Honam University CPUs zInput and output. zSupervisor mode, exceptions, traps. zCo-processors.

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Presentation on theme: "IO - 1Embedded Systems Lab./Honam University CPUs zInput and output. zSupervisor mode, exceptions, traps. zCo-processors."— Presentation transcript:

1 IO - 1Embedded Systems Lab./Honam University CPUs zInput and output. zSupervisor mode, exceptions, traps. zCo-processors.

2 IO - 2Embedded Systems Lab./Honam University I/O devices zUsually includes some non-digital component. zTypical digital interface to CPU: CPU status reg data reg mechanism

3 IO - 3Embedded Systems Lab./Honam University Motorola 16-bit Microcontroller MC68HC16Z1 – 16-bit CPU, SIM, GPT, QSM, ADC, RAM. Powerful, complex modules w register banks z Intermodule Bus z 24-bit address bus, 16-bit data bus; External Bus shared with peer processors z7 level Extl Interrupts z8 Analog Inputs, Event capture and assertion Timer Inputs/outputs, Synchronous and Asynchronous Serial Communication;

4 IO - 4Embedded Systems Lab./Honam University Application: 8251 UART zUniversal asynchronous receiver transmitter (UART) : provides serial communication. z8251 functions are integrated into standard PC interface chip. zAllows many communication parameters to be programmed.

5 IO - 5Embedded Systems Lab./Honam University Serial communication zCharacters are transmitted separately: time bit 0bit 1bit n-1 no char start stop...

6 IO - 6Embedded Systems Lab./Honam University Serial communication parameters zBaud (bit) rate. zNumber of bits per character. zParity/no parity. zEven/odd parity. zLength of stop bit (1, 1.5, 2 bits).

7 IO - 7Embedded Systems Lab./Honam University 8251 CPU interface CPU 8251 status (8 bit) data (8 bit) serial port xmit/ rcv

8 IO - 8Embedded Systems Lab./Honam University Programming I/O zTwo types of instructions can support I/O: yspecial-purpose I/O instructions; ymemory-mapped load/store instructions. Intel x86 provides in, out instructions. Most other CPUs use memory-mapped I/O. zI/O instructions do not preclude memory- mapped I/O.

9 IO - 9Embedded Systems Lab./Honam University ARM memory-mapped I/O zDefine location for device: DEV1 EQU 0x1000 zRead/write code: LDR r1,#DEV1 ; set up device adrs LDR r0,[r1] ; read DEV1 LDR r0,#8 ; set up value to write STR r0,[r1] ; write value to device WHY ACCESS THESE REGISTERS?

10 IO - 10Embedded Systems Lab./Honam University SHARC memory mapped I/O zDevice must be in external memory space (above 0x400000). zUse DM to control access: I0 = 0x400000; M0 = 0; R1 = DM(I0,M0);

11 IO - 11Embedded Systems Lab./Honam University Peek and poke zTraditional HLL interfaces: int peek(char *location) { return *location; } void poke(char *location, char newval) { (*location) = newval; }

12 IO - 12Embedded Systems Lab./Honam University Busy/wait output zSimplest way to program device. yUse instructions to test when device is ready. current_char = mystring; while (*current_char != \0) { poke(OUT_CHAR,*current_char); while (peek(OUT_STATUS) != 0); current_char++; } Pg Dev Addr, String

13 IO - 13Embedded Systems Lab./Honam University Simultaneous busy/wait input and output while (TRUE) { /* read */ while (peek(IN_STATUS) == 0); achar = (char)peek(IN_DATA); Poke (IN_STATUS,0); /* write */ poke(OUT_DATA,achar); poke(OUT_STATUS,1); while (peek(OUT_STATUS) != 0); }

14 IO - 14Embedded Systems Lab./Honam University Interrupt I/O zBusy/wait is very inefficient. CPU can t do other work while testing device. yHard to do simultaneous I/O. zInterrupts allow a device to change the flow of control in the CPU. yCauses subroutine call to handle device.

15 IO - 15Embedded Systems Lab./Honam University Interrupt interface CPU status reg data reg mechanism PC intr request intr ack data/address IR

16 IO - 16Embedded Systems Lab./Honam University Interrupt behavior zBased on subroutine call mechanism. zInterrupt forces next instruction to be a subroutine call to a predetermined location. yReturn address is saved to resume executing foreground program.

17 IO - 17Embedded Systems Lab./Honam University Interrupt physical interface zCPU and device are connected by CPU bus. zCPU and device handshake: ydevice asserts interrupt request; yCPU asserts interrupt acknowledge when it can handle the interrupt.

18 IO - 18Embedded Systems Lab./Honam University Example: character I/O handlers void input_handler() { achar = peek(IN_DATA); gotchar = TRUE; poke(IN_STATUS,0); } void output_handler() { } Global Parameters to communicate with foreground program

19 IO - 19Embedded Systems Lab./Honam University Example: interrupt-driven main program main() { while (TRUE) { if (gotchar) { poke(OUT_DATA,achar); poke(OUT_STATUS,1); gotchar = FALSE; } Foreground program: still no useful work

20 IO - 20Embedded Systems Lab./Honam University Example: interrupt I/O with buffers zQueue for characters: headtail headtail a Example 3-6, Pg 114. Foreground: useful work Last spot unused

21 IO - 21Embedded Systems Lab./Honam University Buffer-based input handler void input_handler() { char achar; if (full_buffer()) error = 1; else { achar = peek(IN_DATA); add_char(achar); } poke(IN_STATUS,0); if (nchars == 1) { poke(OUT_DATA,remove_char(); poke(OUT_STATUS,1); } } Only to start off character outputting

22 IO - 22Embedded Systems Lab./Honam University I/O sequence diagram :foreground:input:output:queue empty a b bc c

23 IO - 23Embedded Systems Lab./Honam University Debugging interrupt code zWhat if you forget to change registers? yForeground program can exhibit mysterious bugs. yBugs will be hard to repeat---depend on interrupt timing. z Book Example 3-7, Page 119: Interrupt Handler changes value of j in the foreground matrix program. HOW? Is it time sensitive? Can we overcome the problem?

24 IO - 24Embedded Systems Lab./Honam University Priorities and vectors zTwo mechanisms allow us to make interrupts more specific: yPriorities determine what interrupt gets CPU first. yVectors determine what code is called for each type of interrupt. zMechanisms are orthogonal: most CPUs provide both.

25 IO - 25Embedded Systems Lab./Honam University Prioritized interrupts CPU device 1device 2device n R0 R1.. Rn interrupt acknowledge IR0 IR1 IRn

26 IO - 26Embedded Systems Lab./Honam University Interrupt prioritization zMasking: interrupt with priority lower than current priority is not recognized until pending interrupt is complete. zNon-maskable interrupt (NMI): highest-priority, never masked. yOften used for power-down.

27 IO - 27Embedded Systems Lab./Honam University Example: Prioritized I/O :interrupts:foreground:A:A:B:B:C:C B A,B C A

28 IO - 28Embedded Systems Lab./Honam University Interrupt vectors zAllow different devices to be handled by different code. zInterrupt vector table: handler 0 handler 1 handler 2 handler 3 Interrupt vector table head

29 IO - 29Embedded Systems Lab./Honam University Interrupt vector acquisition :CPU:device receive request receive ack receive vector

30 IO - 30Embedded Systems Lab./Honam University Generic interrupt mechanism intr? N Y Assume priority selection is handled before this point. N ignore Y ack vector? Y Y N timeout? Y bus error call table[vector] intr priority > current priority? continue execution

31 IO - 31Embedded Systems Lab./Honam University Interrupt sequence zCPU acknowledges request. zDevice sends vector. zCPU calls handler. zSoftware processes request. zCPU restores state to foreground program.

32 IO - 32Embedded Systems Lab./Honam University Sources of interrupt overhead zHandler execution time. zInterrupt mechanism overhead. zRegister save/restore. zPipeline-related penalties. zCache-related penalties.

33 IO - 33Embedded Systems Lab./Honam University ARM interrupts zARM7 supports two types of interrupts: yFast interrupt requests (FIQs). yInterrupt requests (IRQs). zInterrupt table starts at location 0.

34 IO - 34Embedded Systems Lab./Honam University ARM interrupt procedure zCPU actions: ySave PC. Copy CPSR to SPSR. yForce bits in CPSR to record interrupt. yForce PC to vector. zHandler responsibilities: yRestore proper PC. yRestore CPSR from SPSR. yClear interrupt disable flags.

35 IO - 35Embedded Systems Lab./Honam University ARM interrupt latency zWorst-case latency to respond to interrupt is 27 cycles: yTwo cycles to synchronize external request. yUp to 20 cycles to complete current instruction. yThree cycles for data abort. yTwo cycles to enter interrupt handling state.

36 IO - 36Embedded Systems Lab./Honam University SHARC interrupt structure zInterrupts are vectored and prioritized. zPriorities are fixed: reset highest, user SW interrupt 3 lowest. zVectors are also fixed. Vector is offset in vector table. Table starts at 0x20000 in internal memory, 0x40000 in external memory.v

37 IO - 37Embedded Systems Lab./Honam University SHARC interrupt sequence Start: must be executing or IDLE/IDLE Output appropriate interrupt vector address. 2. Push PC value onto PC stack. 3. Set bit in interrupt latch register. 4. Set IMASKP to current nesting state.

38 IO - 38Embedded Systems Lab./Honam University SHARC interrupt return Initiated by RTI instruction. 1. Return to address at top of PC stack. 2. Pop PC stack. 3. Pop status stack if appropriate. 4. Clear bits in interrupt latch register and IMASKP.

39 IO - 39Embedded Systems Lab./Honam University SHARC interrupt performance Three stages of response: y1 cycle: synchronization and latching; y1 cycle: recognition; y2 cycles: brancing to vector. Total latency: 3 cycles. Multiprocessor vector interrupts have 6 cycle latency.

40 IO - 40Embedded Systems Lab./Honam University Supervisor mode zMay want to provide protective barriers between programs. yAvoid memory corruption. zNeed supervisor mode to manage the various programs. zSHARC does not have a supervisor mode.

41 IO - 41Embedded Systems Lab./Honam University ARM supervisor mode zUse SWI instruction to enter supervisor mode, similar to subroutine: SWI CODE_1 zSets PC to 0x08. zArgument to SWI is passed to supervisor mode code. zSaves CPSR in SPSR.

42 IO - 42Embedded Systems Lab./Honam University Exception zException: internally detected error. zExceptions are synchronous with instructions but unpredictable. zBuild exception mechanism on top of interrupt mechanism. zExceptions are usually prioritized and vectorized.

43 IO - 43Embedded Systems Lab./Honam University Trap zTrap (software interrupt): an exception generated by an instruction. yCall supervisor mode. zARM uses SWI instruction for traps. zSHARC offers three levels of software interrupts. yCalled by setting bits in IRPTL register.

44 IO - 44Embedded Systems Lab./Honam University Co-processor zCo-processor: added function unit that is called by instruction. yFloating-point units are often structured as co- processors. zARM allows up to 16 designer-selected co- processors. yFloating-point co-processor uses units 1 and 2.

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