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Torino, Italy – June 27th, 2013 A2B: AN I NTEGRATED F RAMEWORK FOR D ESIGNING H ETEROGENEOUS AND R ECONFIGURABLE S YSTEMS C. Pilato, R. Cattaneo, G. Durelli,

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Presentation on theme: "Torino, Italy – June 27th, 2013 A2B: AN I NTEGRATED F RAMEWORK FOR D ESIGNING H ETEROGENEOUS AND R ECONFIGURABLE S YSTEMS C. Pilato, R. Cattaneo, G. Durelli,"— Presentation transcript:

1 Torino, Italy – June 27th, 2013 A2B: AN I NTEGRATED F RAMEWORK FOR D ESIGNING H ETEROGENEOUS AND R ECONFIGURABLE S YSTEMS C. Pilato, R. Cattaneo, G. Durelli, A.A. Nacci, M.D. Santambrogio, D. Sciuto Politecnico di Milano Dipartimento di Elettronica, Informazione e Bioingegneria, Italy NASA/ESA C ONFERENCE ON A DAPTIVE H ARDWARE AND S YSTEMS (AHS 2013)

2 Torino, Italy – June 27th, Motivations  The design of reconfigurable systems is a difficult task Interactions between the different phases have to be taken into account  Decisions in the frontend phase may highly affect the backend implementation: iterative exploration E.g.: Mapping onto reconfigurable regions and floorplacing of the tasks may generate low-quality solutions due to a wrong partitioning or assignment of implementations  Currently, the optimal design methodology (and the number of its iterations) is not known in advance A2B is an ongoing project at Politecnico di Milano to assist the design of such complex systems

3 Torino, Italy – June 27th, Agenda  Framework Overview Design Space Exploration Solution Generation  Preliminary Results – Test Case  Conclusions and Future Work

4 Torino, Italy – June 27th, Framework Overview Evaluation Exploration  Inputs: Information about the target device (.XML) Application source files (.C) plus custom pragma for additional information (e.g., task level parallelism/kernels)  Decision Making (Exploration): Task graph generation Library generation Mapping, Scheduling, Floorplacing Architectural modification  Refinement (Evaluation): Specification of the platform details Code generation for target platform  Output: Project files ready for the synthesis with back-end tools

5 Torino, Italy – June 27th, XML Exchange Format  The entire project can be represented through an XML file Architecture: components’ characteristics (e.g., reconfigurable regions), … Applications: source code files and profiling information Library: task implementations with the characterization (time, resources,...) Partitions: task graph, mapping and scheduling, …  It allows a modular organization of the framework, but also the sharing of information among the different phases The phases can be applied in any order to progressively optimize the design The designer can perform as many iterations as he/she wants to refine the solution  Specific details of the target architecture are taken into account only in the refinement phase (interactions with backend tools)

6 Torino, Italy – June 27th, Task Graph Generation  Application source code files can be analyzed to extract the task graphs Profiling information can drive the generation of such solutions  Task graph will be then specified in the XML file as processing nodes connected by data transfers Currently they can be designed by hand, but automated methodologies for automatic extraction will be investigated in the future Transformations to improve the description by splitting/merging the tasks #pragma omp task void threshold(unsigned char *o1,unsigned char *r, unsigned char t, int * p){ nt DIMH = p[0]; int minH1 = p[1]; int maxH1 = p[2]; int minV1 = p[3]; int maxV1 = p[4]; for(v=minV1;vthresh){ result[v*DIMH*BPP+h*BPP]=255; result[v*DIMH*BPP+h*BPP+1]=255; result[v*DIMH*BPP+h*BPP+2]=255; } else{ result[v*DIMH*BPP+h*BPP]=0; result[v*DIMH*BPP+h*BPP+1]=0; result[v*DIMH*BPP+h*BPP+2]=0; }

7 Torino, Italy – June 27th, Library Generation: a collection of implementations  LLVM-based compiler to extract the dataflow graph of each task Estimation of required resources (including bit-width analysis) [IMP] Interaction with HLS synthesis tools to obtain more accurate results  Generated implementations are then store in the XML file to offer opportunities to the mapping phase and information to the floorplacer Politecnico di Milano/Imperial College of London joint effort to integrate High Level Analysis techniques into the toolchain A Framework for Effective Exploitation of Partial Reconfiguration in Dataflow Computing – R.Cattaneo, X. Niu, C. Pilato, T.Becker, W.Luk, M. D. Santambrogio (to appear in ReCoSoC13)

8 Torino, Italy – June 27th, Mapping, Scheduling and Floorplacing  We generate one or more configurations where each task of the applications is analyzed and assigned (via Mapping, Scheduling and Floorplanning – M/S/FP) to An available and admissible implementation A component of the architecture (e.g., processor or reconfigurable region)  This allows to “share” implementations across different tasks (hardware sharing) move a task implementation to another processing element at run-time (task relocation)

9 Torino, Italy – June 27th, Architecture Exploration  An additional step can be included to explore the target architecture Adding/removing processing elements (reconfigurable regions) Modifying their parameters Determining the proper interconnection topology  It can iteratively affect: task graph transformations and library generation mapping and floorplacing: modification to the computational resources (especially the number of reconfigurable regions)  It allows a progressive and iterative refinement of the solution and a concurrent customization of both architecture and application E.g.: mapping and floorplacing can suggest which resources should be added

10 Torino, Italy – June 27th, Supported Platforms  Virtex-5 XC5VLX110T (embedded) Two XCF32P Platform Flash PROMs (32Mbyte each) SystemACE™ Compact Flash configuration controller 64-bit wide 256Mbyte DDR2 small outline DIMM (SODIMM)  Maxeler MaxWorkstation (HPC system) Intel i7 16GB RAM, 500GB HDD Max3 dataflow engine (DFE) Virtex 6 SX475T FPGA, 24GB memory DFE connected to CPU via PCI Express XUPV5 Reconf. Area DDR2 (256MB) CPU0 CPU1 CPU MAX3 DFE DRAM (16GB) Interface FPGA Compute FPGA DRAM (24GB)

11 Torino, Italy – June 27th, Target-Dependent Code Generation CPU Compiler.c.xml Bitstream Generation HLS (MaxJ-VHDL) -Source code for CPU -DFGs for HW tasks -Mapping configurations Bitstream Generation exec bin bit Manual VHDL Implementations DFG-C HLS (C-VHDL) Manual MaxJ Implementations FPGA-based embedded system MaxWorkstation The code can be always further optimized by hand; e.g., glue code for data transfers MaxIDE DFG-MaxJ

12 Torino, Italy – June 27th, Graphical User Interface (GUI)  Practical GUI to support the designer, to limit the errors in the interactions with the XML and to allow custom design methodologies

13 Torino, Italy – June 27th, Preliminary results: edge detection  Edge detection application: 4 stages of computation C + custom #pragmas based description Extracted taskgraph and corresponding DFG of first stage (Scale, 1x parallelism)  We generate 4 implementations with different levels of parallelism and resource consumption for each of the 4 tasks of the application “parallelism X”: X pixels processed at once  Maxeler Backend

14 Torino, Italy – June 27th, Experimental Results / 1  Static vs reconfigurable design (both extracted using the framework) R0: S,T R1: B,E Task Name Area Occupation S664 B64 E7680 T7376 Region NameFinal Area Occupation R0max(664,64)=664 R1max(7680,7376)=7680 Total area consumption =8344  Reconfigurable (parallelism 8) Task Name Area Occupation S664 B64 E7680 T7376 Region NameFinal Area Occupation Total area consumption = 7876  Static (parallelism 4) IP0: S IP1: B IP2: E IP3: T  We limit the available area to 10klut and implement the most performing design

15 Torino, Italy – June 27th, Experiment Results / 2  Reconfiguration time is automatically masked (when possible)  Partial Reconfiguration improves performance of application via resource multiplexing

16 Torino, Italy – June 27th, Conclusions and Future Work  A2B is a modular framework to design reconfigurable systems Easy to plug alternative methods for each of the phase Possibility to perform progressive refinement of both application and architecture  A2B is becoming part of a larger project (ASAP – Advanced Synthesis of Applications and Platforms) Refinement will also include the generation of SystemC TLM models of the target system for (co-)simulation and early validation More architectural templates Closer interaction with actual synthesis (e.g., high-level synthesis) Automated methodologies to accelerate the design

17 Torino, Italy – June 27th, 2013 Thank you! Riccardo Cattaneo the European Community’s Seventh Framework Programme, FASTER project. Research partially funded by the European Community’s Seventh Framework Programme, FASTER project.


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