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# Q R Flip Flops ATS 電子部製作 S Q For a NOR gate, the output would be logic 1 only when both the inputs are 0 : AB 0 0 0 1 10 F 1 0 0 011 A B F.

## Presentation on theme: "Q R Flip Flops ATS 電子部製作 S Q For a NOR gate, the output would be logic 1 only when both the inputs are 0 : AB 0 0 0 1 10 F 1 0 0 011 A B F."— Presentation transcript:

Q R Flip Flops ATS 電子部製作 S Q

For a NOR gate, the output would be logic 1 only when both the inputs are 0 : AB 0 0 0 1 10 F 1 0 0 011 A B F

S R Q Q Let’s examine the relationship between the inputs (S, R)and outputs (Q, Q)of a circuit formed by a pair of cross-coupled Nor gates: 1 0 0 0 1 0 1 0 0 0 1 1 0 S R Q Q

S R Q Q Let’s examine the relationship between the inputs (S, R)and outputs (Q, Q)of a circuit formed by a pair of cross-coupled Nor gates: S R Q Q 1 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 0 1 0

S R Q Q Let’s examine the relationship between the inputs (S, R)and outputs (Q, Q)of a circuit formed by a pair of cross-coupled Nor gates: S R Q Q 1 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0

S R Q Q Let’s examine the relationship between the inputs (S, R)and outputs (Q, Q)of a circuit formed by a pair of cross-coupled Nor gates: S R Q Q 1 0 0 0 1 0 0 1 ? ? ? 0 0 0 1 1 1 0 0 0 0 ? 0 0 ? ?

Conclusion S R Q Q 1 0 0 0 1 0 0 1 0 0 0 1 1 1 0 0 0 0 ? ? SET RESET Unchanged Ambiguous, to be avoided F S R Q Q

Alternatively, cross-coupled NAND gates make a Flip-Flop responding to logic 0: S R Q Q 0 1 1 0 1 0 0 1 0 0 ambiguous 1 1 unchanged F S R Q Q S R Q Q

Clocked FF S R CK Q Q S R Q Q Changes state only on positive clock transition. Changes state only on negative clock transition.

JJ K-FF J K CK Q Q J K Q 0 0 unchanged 1 0 1* 0 1 0* 1 1 toggles* * Upon positive clock transition

D -FF S R CK Q Q D J K Q Q D D Q 0 0* * Upon positive clock transition 1 1*

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