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Green Transistor for 10X Lower IC Power ?

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Presentation on theme: "Green Transistor for 10X Lower IC Power ?"— Presentation transcript:

1 Green Transistor for 10X Lower IC Power ?
Chenming Hu University of California, Berkeley Supported by: DARPA STEEP, FCRP-MSD

2 Electronics Infrastructure
the world enabled IC chips fabs transistors electronic systems $ 6/2009 Chenming Hu

3 Expectation: ICs will be even more..
Affordable (size reduction..): manufacturing, device physics limit,… Useful (speed, density..): natural human interface, bio-medical sensing… Usable (low power): heat management, portability, global energy conservation… 6/2009 Chenming Hu

4 Power Consumption Problems
Thermal management/package issues may limit integration density. IC usage of electricity at an inflection point. ICs use a few % of world’s electricity today and growing exponentially. Power per chip is growing. IC units in use also growing. Need to reduce IC power consumption with architecture and circuit innovations, and a low voltage transistor. 6/2009 Chenming Hu

5 IC Power Consumption Rising Much Faster Than Past Trend
Because power consumption Vdd2 and Vdd (operation voltage) scaling has slowed. Technology Node 0.25 μm 0.18 μm 0.13 μm 90 nm 65 nm 45 nm 32 nm 22 nm 16 nm Vdd 2.5 V 1.8 V 1.3 V 1.2 V 1.1 V 1.0 V 0.9 V 0.8 V 0.7 V High Performance ITRS Roadmap 6/2009 Chenming Hu

6 Why Vdd scaling slowed We used to control power by scaling Vdd and maintain good speed by reducing Tox. But, Tox can not be reduced much more, not even with high-k dielectrics. But new materials will raise the mobility, μ Speed transistor current μ ( Vdd – Vt ) / Tox 1.2 nm SiO2 6/2009 Chenming Hu

7 New material, e.g. Ge film on Si substrate
Oxide Silicon Drain Source Gate 3nm Ge film Industry is also funding InGaAs, InAs, and graphene MOSFET research. 6/2009 Chenming Hu

8 How to Reduce Power by 20X Two steps to reduce Vdd to 0.2V for 20x power reduction? Reduce Vdd – Vt to < 0.15V with high-mobility-channel material (Ge, III-V, graphene...), etc. Reduce Vt to 50mV. But, there is the fundamental 60mV/decade turn-off limit ….. 6/2009 Chenming Hu

9 Ioff Limit - 60mV/decade Swing
Lowering Vt by 60mV increases the leakage current (power) by 10 times. Vt Drain Current, I DS (A/ m m) Gate Voltage, V GS (V) 0.0 0.3 0.6 0.9 10 -11 -9 -7 -5 -3 Lower Vt Source: Intel Corporation 9 6/2009 Chenming Hu 9

10 The “fundamental” 60mV/decade Limit
Ev COX VG Source Channel Drain Electrons go over a potential barrier. Leakage current is determined by the Boltzmann distribution or 60 mV/decade, limiting MOSFET, bipolar, graphene MOSFET… How to overcome the limit: Let electrons go through the energy barrier, not over it  tunneling 10 6/2009 Chenming Hu

11 Semiconductor Band-to-Band Tunneling
EC EV A known mechanism of leakage current since 1985. J. Chen, P. Ko, C. Hu, IEDM 1985 Called Gate Induce Drain Leakage (GIDL) because the current depends on the gate voltage. 6/2009 Chenming Hu

12 Basic Tunnel Transistor Structure
P+ Drain N+ Source P - Some references W. Reddick, G. Amaratunga, Appl. Phys. Letters, vol. 67, 1994. W. M. Reddick, et al., Appl. Phys. Lett., vol. 67(4), pp , 1995. C. Aydin, A. Zaslavsky, et al., Appl. Phys. Lett., vol. 84(10), pp , 2004. WY. Choi et al., Tech. Dig. Int. Electron Device Meet, pp , 2005. K. K Bhuwalka, et al., Jpn. J. of Appl. Phys., vol. 45(4B), pp , 2006. Th. Nirschl, et al., Electron Device Letters, vol. 28(4), p. 315, 2007. ~100X less current than MOSFET Need a more optimal tunneling transistor structure. 12 6/2009 Chenming Hu

13 Green Transistor (gFET)--Simulation
P+ Buried Oxide P+ Pocket P - C. Hu et al, 2008 VLSI-TSA, p.14, April, 2008 S D Simulated carrier generation rates Hole flow Electron flow N+ Source P+ Pocket Gate P+ Drain Energy band diagram Large field, good capacitive coupling between gate and pocket, abrupt turn-on due to over-lap of valence/conduction bands, adjustable tun-on voltage. 13 6/2009 Chenming Hu

14 gFET vs Basic Tunnel FET-simulation
EOT= 1 nm VDD=1V Lg=40nm EOT= 4.5 nm VDD=4V gFET Drain Current, IDS (A/µm) Basic Tunnel FET * Gate Voltage, VGS (V) C. Hu et al, 2008 VLSI-TSA, p.14, April, 2008 * K. K Bhuwalka, et al., Jpn. J. of Appl. Phys., vol. 45(4B), pp , 2006 6/2009 Chenming Hu

15 Simulated Id-Vd of 0.5V Ge gFET
Drain-Source Voltage, VDS (V) Drain Current, IDS (µA/µm) EOT=0.5nm Good output resistance and DIBL. Lg = 40nm C. Hu et al, 2008 VLSI-TSA, p.14, April, 2008 6/2009 Chenming Hu

16 Vdd (Power) Scaling Path: Reduce Band Gap
- 11 10 09 08 07 06 05 04 03 02 0.0 0.2 0.4 0.6 0.8 1.0 Ids (A/um) Eg=0.36eV (InAs) Eg=0.69eV (Ge) Silicon Eg=0.36eV, Vdd=0.2V, EOT=5 Å, CV/I=0.42pS Eg=0.69eV, Vdd=0.5V, EOT=7 Å, CV/I=2.2pS Eg=1.1eV, Vdd=1V, EOT=10 Å, CV/I=4.2pS Gate Voltage, VGS (V) Drain Current, IDS (µ/µm) Lg=40nm C. Hu et al, 2008 VLSI-TSA, p.14, April, 2008 6/2009 Chenming Hu 16

17 Hetero-tunneling gFET
In lieu of low Eg semiconductor, a heterojunction can provide a very small effective tunneling band gap, Egeff. Gate Oxide Gate A B Egeff P+ Source N+ Drain B Substrate Gate A EC EV Egeff is 0.3eV for Si/Ge hetero-tunneling gFET. A. Bownder et al., 8th International workshop Junction Technology, Extended Abstracts , p.93, Also IEEE Silicon Nanoelectronics Workshop, 2008. 6/2009 Chenming Hu

18 Compound Semiconductors
Egeff Wide choices of heterojunction materials, band engineering and strain engineering. Example: InAs-AlGaSb provides tunable Egeff from positive to negative values. Very low voltage gFET may be possible. 18 6/2009 Chenming Hu 18

19 Ge-Source Tunnel Transistor
SiO2 Si N+ Si Drain P+ Ge Gate ID [A/mm] Experiment Model VGS [V] S [mV/dec] ID [A/mm] VD=0.5V LG=5mm W=0.33mm Es = |VGS+Vtunnel|/(Tox ege/eox) Vtunnel ~ 0.6V S. Kim et al., VLSI Tech Symp., 2009

20 Green’s Function Based Simulation
Sayeef Salahudin

21 Summary ICs use of world’s electricity is several % and growing fast.
A low voltage transistor can slow the growth. Green Transistor may potentially provide orders-of-magnitude IC power reduction. 6/2009 Chenming Hu

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