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Chapter 4 Combinational Logic

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4.1 Introduction Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of logic gates whose outputsat anytime are determined from only the present combinationof inputs. 2

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4.2 Combinational Circuits Logic circuits for digital system Sequential circuits contain memory elements the outputs are a function of the current inputs and the state of the memory elements the outputs also depend on past inputs 3

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A combinational circuits 2possible combinations of input values n Combinational circuits Combinatixnal xoxic Circuit n inputm output variables 4 Specific functions Adders, subtractors, comparators, decoders, encoders, andmultiplexers

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4-3 Analysis Procedure A combinational circuit make sure that it is combinational not sequential No feedback path derive its Boolean functions (truth table) designverification

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A straight-forward procedure = AB+AC+BCF 2 T 1 = A+B+C 6 1 T T = ABC = F2'T1 = T3+T2F

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F = (AB+AC+BC)'(A+B+C)+ABC = (A'+B')(A'+C‘)(B'+C')(A+B+C)+ABC = (A'+B'C')(AB'+AC'+BC'+B'C)+ABC = A'BC'+A'B‘C+AB‘C'+ABC = T+T=F=F'T+ABC 7

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The truth table 8

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4-4 Design Procedure The design procedure ofcombinational circuits State the problem (system spec.) determine the inputs and outputs the inputand output variables are assigned symbols derivethe truth table xerive the simplified Boolxan functionx draw the logic diagram and verify the correctness 9 derive the simplifi edb oolean functions

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code conversion example BCD to excess-3 code Thetruth table 11

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The maps 12

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The simplified functions z = D' y = CD +C'D‘ x = B'C + B‘D+BC'D' w = A+BC+BD z = D' y = CD +C'D'= CD + (C+D)' x = B'C +B'D+BC'D‘ = B'(C+D) +B(C+D)' w = A+BC+BD 13 Another implementation

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The logic diagram 14

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4-5Binary Adder-Subtractor Half adder = 0 ; = 1 ; = 1 ;1+ 1 = 10 two input variables: x, y two output variables: C (carry), S (sum) truth table 15

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S = x'y+xy' C = xy the flexibility for implementation S=x y S = (x+y)(x'+y') S = (C+x'y')' C = xy = (x'+y')x 16 S‘= xy+x'y'

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Functional Block: Full-Adder A full adder is similar to a half adder, but includes a carry-in bit from lower stages. Like the half-adder, it computes a sum bit, S and a carry bit, C. For a carry-in (Z) of 0, it is the same as the half-adder: For a carry- in (Z) of 1: Z0000 X Y C S Z1111 X Y C S

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Full-Adder the arithmetic sum of three inputbits three input bits x, y: two significant bits z: the carrybit from the previous lower significant bit Two outputbits: C, S 18

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S = x'y'z+x'yz'+ xy'z'+xyz C = xy+ xz + yz S = z (x y) = z'(xy'+x‘y)+z(xy'+x'y)' = z‘xy'+z'x'y+z(xy+x‘y') = xy'z'+x'yz'+xyz+x'y'z C = z(xy'+x'y)+xy = xy'z+x'yz+ xy 20

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Binary adder 21

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Binary subtractor A-B = A+(2’s complement of B) 4-bit Adder-subtractor M=0, A+B; M=1, A+B’+1 26

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Overflow The storage is limited Add two positive numbers and obtain a negative number Add two negative numbers and obtain a positive number V = 0, no overflow; V = 1, overflow 27 Example:

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4-6 Decimal Adder Add twoBCD's 9 inputs: two BCD's and one carry-in 5 outputs: one BCD and one carry-out Design approaches A truth table with 2^9 entries the sum <= = 19 binary to BCD useuinary full Adders 24

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BCD Adder: The truthTable 25

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Modifications are needed if the sum > 9 C = 1 K = 1 Z Z 8484 Z= Z moxification: (10) d or +6 modification: (10) d or +6 C = K +ZZ+ ZZ

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Block diagram 27

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Binary Multiplier Partial products – AND operations fig Two-bit by two-bit binary multiplier. 28

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4-bit by 3-bit binary multiplier Digital Circuits Fig Four-bit by three-bit binary multiplier. 29

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4-9 Decoder A n-to-m decoder a binary code ofnbits = 2distinct information n n input variables;up to 2outputlines only on e output can be active (high) a t any time n 30

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An implementation Digital Circuits 38 Fig Three-to-eight-line decoder. 31

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Combinational logicimplementation eachoutput = a minterm use a decoder and an external OR gate to implement any Boolean function of n input variables 32

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Demultiplexers a decoder with an enable input receive informationin a single line and transmits itin one of2possible output lines n Fig Two-to-four-line decoder with enable input 33

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Decoder Examples D 0 = m 0 = A 2 ’A 1 ’A 0 ’ D 1 = m 1 = A 2 ’A 1 ’A 0 …etc 3-to-8-Line Decoder: example: Binary-to-octal conversion.

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Expansion two 3-to-8decoder: a 4-to-16 deocder a 5-to-32decoder? Fig 16 decoder constructed with two 3x8 decoders 35

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Decoder Expansion - Example 2 Construct a 5-to-32-line decoder using four 3-8-line decoders with enable inputs and a 2-to-4-line decoder. D 0 – D 7 D 8 – D 15 D 16 – D 23 D 24 – D 31 A3A4A3A4 A0A1A2A0A1A2 2-4-line Decoder 3-8-line Decoder E E E E

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Combination Logic Implementation each output = a minterm use a decoder andan external OR gate to implement any Boolean function of n input variables A full-adder S(x,y,z)= (1,2,4,7) C(x,y,z)= (3,5,6,7)C(x,y,z)= (3,5,6,7) Fig Implementation of a full adder with1decoder 37

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two possible approachesusingdecoder OR(minterms of F): k inputs NOR(minterms of F'): 2 k inputs In general, it isnot apractical implementation n 38

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4-10 Encoders The inverse function of decoder a decoder zDDDD y D DDD xDDDD The encoder can be implemented with three OR gates. 39

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An implementation limitations illegal input: e.g. D 3636 The output = 111 (¹3 and ¹6) =Dx1 40

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Priority Encoder resolve the ambiguity of illegal inputs only one of theinput is encoded D D 3 0 X: don't-careconditions V: valid output indicator has the highest priority has the lowest priority 41

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■The maps for simplifying outputs x and y fig Maps for a priority encoder 42

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■Implementation of priority Fig Four-input priority encoder xx yy DD DD V D DDD

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4-11 Multiplexers select binary information from one of many input lines and direct itto a single output line 2input lines, n selection lines and oneoutput line e.g.: 2-to-1-line multiplexer n Fig Two-to-one-line multiplexer 44

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4-to-1-line multiplexer Fig Four-to-one-line multiplexer 45

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Note n-to- 2decoder n add the 2inputlines to eachAND gate OR(all AND gates) an enable input (anoption) n 46

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Fig Quadruple two-to-one-line multiplexer 47

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Boolean function implementation MUX: a decodersan OR gate 2 -to-1 MUX can implement any Boolean function of n input variable n n of these variables: the selection lines the remaining variable: the inputs a better solution: implement any Boolean function of n+1 input variable 48

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an example: F(A,B,C) = (1,2,6,7) Fig Implementing a Boolean function with a multiplexer 49

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procedure: assign anordering sequence of the inputvariable the rightmost variable(D) will be used forthe input lines assign the remaining n-1 variables to the selection 0 determine the input lines lines w.r.t. their corresponding sequ consider a pairof consecutive minterms starting from m 50 Lines with construct the truth table

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Example: F(A, B, C, D) = (1, 3, 4, 11, 12,13, 14, 15) Fig Implementing a four-input functionwith a multiplexer 51

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Three-state gates A multiplexer can be constructed with three-state gates Output state: 0, 1, and high-impedance (open ckts) Fig Graphic symbol for a three-state buffer 52

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Example: Four-to-one-line multiplexer Fig Multiplexer with three-state gates 53

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