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Chapter 4 Combinational Logic

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**4.1 Introduction Logic circuits for digital systems may be**

combinational or sequential. A combinational circuit consists of logic gates whose outputs at any time are determined from only the present combination of inputs. 2

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**4.2 Combinational Circuits**

Logic circuits for digital system Sequential circuits contain memory elements the outputs are a function of the current inputs and the state of the memory elements the outputs also depend on past inputs 3

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**Combinational circuits**

A combinational circuits 2 possible combinations of input values n Combinational circuits n input m output Combinatixnal variables variables xoxic Circuit Specific functions Adders, subtractors, comparators, decoders, encoders, and multiplexers 4

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**4-3 Analysis Procedure A combinational circuit**

make sure that it is combinational not sequential No feedback path derive its Boolean functions (truth table) design verification

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**A straight-forward procedure**

= AB+AC+BC 2 T = A+B+C 1 1 T = ABC 2 T = F2'T1 3 F = T3+T2 1 6

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**= (AB+AC+BC)'(A+B+C)+ABC = (A'+B')(A'+C‘)(B'+C')(A+B+C)+ABC **

F = T +T = F 'T +ABC = (AB+AC+BC)'(A+B+C)+ABC = (A'+B')(A'+C‘)(B'+C')(A+B+C)+ABC = (A'+B'C')(AB'+AC'+BC'+B'C)+ABC = A'BC'+A'B‘C+AB‘C'+ABC 7

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The truth table 8

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**4-4 Design Procedure The design procedure of combinational circuits**

State the problem (system spec.) determine the inputs and outputs the input and output variables are assigned symbols derive the truth table x derive the simplifi erive the simplified Bool ed b oolean functions xan functionx draw the logic diagram and verify the correctness 9

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**code conversion example**

BCD to excess-3 code The truth table 11

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The maps 12

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**The simplified functions**

z = D' y = CD +C'D‘ x = B'C + B‘D+BC'D' w = A+BC+BD Another i mplementation z = D' y = CD +C'D' = CD + (C+D)' x = B'C + B'D+BC'D‘ = B'(C+D) +B(C+D)' w = A+BC+BD 13

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The logic diagram 14

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**4-5 Binary Adder-Subtractor**

Half adder 0 + 0 = 0 ; = 1 ; = 1 ; = 10 two input variables: x, y two output variables: C (carry), S (sum) truth table 15

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**the flexibility for implementation**

S = x'y+xy' C = xy the flexibility for implementation S=xÅy S = (x+y)(x'+y') S‘= xy+x'y' S = (C+x'y')' C = xy = (x'+y')x 16

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**Functional Block: Full-Adder**

A full adder is similar to a half adder, but includes a carry-in bit from lower stages. Like the half-adder, it computes a sum bit, S and a carry bit, C. For a carry-in (Z) of , it is the same as the half-adder: For a carry- in (Z) of 1: Z X 1 + Y + 0 + 1 C S 0 1 1 0 Z 1 X + Y + 0 + 1 C S 0 1 1 0

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**the arithmetic sum of three input bits three input bits**

Full-Adder the arithmetic sum of three input bits three input bits x, y: two significant bits z: the carry bit from the previous lower significant bit Two output bits: C, S 18

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**S = x'y'z+x'yz'+ xy'z'+xyz C = xy + xz + yz S = zÅ (xÅy)**

C = xy + xz + yz S = zÅ (xÅy) = z'(xy'+x‘y)+z(xy'+x'y)' = z‘xy'+z'x'y+z(xy+x‘y') = xy'z'+x'yz'+xyz+x'y'z C = z(xy'+x'y)+xy = xy'z+x'yz+ xy 20

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Binary adder 21

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**Binary subtractor A-B = A+(2’s complement of B) 4-bit Adder-subtractor**

4-bit Adder-subtractor M=0, A+B; M=1, A+B’+1 26

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**Overflow The storage is limited**

The storage is limited Add two positive numbers and obtain a negative number Add two negative numbers and obtain a positive number V = 0, no overflow; V = 1, overflow Example: 27

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**4-6 Decimal Adder Add two BCD's Design approaches**

9 inputs: two BCD's and one carry-in 5 outputs: one BCD and one carry-out Design approaches use uinary full Adders A truth table with 2^9 entries the sum <= = 19 binary to BCD

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**BCD Adder: The truth Table**

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**Modifications are needed if the sum > 9**

C = 1 K = 1 Z Z = 1 8 4 Z Z = 1 8 2 mo mo d ification: ification: x - - (10) (10) or +6 or +6 d d C = K +Z Z + Z Z

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Block diagram

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**Binary Multiplier Partial products – AND operations fig. 4.15**

– AND operations fig. 4.15 Two-bit by two-bit binary multiplier.

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**4-bit by 3-bit binary multiplier**

Fig. 4.16 Four-bit by three-bit binary multiplier. Digital Circuits

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**4-9 Decoder A n-to-m decoder**

a binary code of n bits = 2 distinct information n n n input variables; up to 2 output lines only one output can be active (high) at any time

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**An implementation Fig. 4.18 Three-to-eight-line decoder. 38**

Digital Circuits 38

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**Combinational logic implementation**

each output = a minterm use a decoder and an external OR gate to implement any Boolean function of n input variables

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**Demultiplexers a decoder with an enable input receive information**

a decoder with an enable input receive information in a single line and transmits it in one of 2 possible output lines n Fig. 4.19 Two-to-four-line decoder with enable input

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**Decoder Examples D0 = m0 = A2’A1’A0’ D1= m1 = A2’A1’A0 …etc**

3-to-8-Line Decoder: example: Binary-to-octal conversion. D0 = m0 = A2’A1’A0’ D1= m1 = A2’A1’A0 …etc

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**Expansion two 3-to-8 decoder: a 4-to-16 deocder a 5-to-32 decoder?**

two 3-to-8 decoder: a 4-to-16 deocder Fig. 4.20 4 16 decoder constructed with two 3 x 8 decoders a 5-to-32 decoder?

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**Decoder Expansion - Example 2**

Construct a 5-to-32-line decoder using four 3-8-line decoders with enable inputs and a 2-to-4-line decoder. A0 A1 A2 3-8-line Decoder E D0 – D7 D8 – D15 D16 – D23 D24 – D31 2-4-line Decoder A3 A4

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**Combination Logic Implementation**

each output = a minterm use a decoder and an external OR gate to implement any Boolean function of n input variables A full-adder S(x,y,z)=S(1,2,4,7) C(x,y,z)= C(x,y,z)= S S (3,5,6,7) (3,5,6,7) Fig. 4.21 Implementation of a full adder with 1 decoder

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**two possible approaches using decoder**

OR(minterms of F): k inputs NOR(minterms of F'): 2 - k inputs n In general, it is not a practical implementation

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**4-10 Encoders The inverse function of decoder a decoder z = D + D + D**

a decoder z = D + D + D + D The encoder can be implemented y = D + D + D + D with three OR gates. x = D + D + D + D

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**An implementation limitations illegal input: e.g. D =D x1**

limitations illegal input: e.g. D =D x1 3 6 The output = 111 (¹3 and ¹6)

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**Priority Encoder resolve the ambiguity of illegal inputs**

only one of the input is encoded D has the highest priority 3 D has the lowest priority X: don't-care conditions V: valid output indicator

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**■ The maps for simplifying outputs x and y**

fig. 4.22 Maps for a priority encoder

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**■ Implementation of priority**

x = Fig. 4.23 D + D 2 3 Four-input priority encoder y= D + D D V = D + D + D + D

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**4-11 Multiplexers select binary information from one of many input**

lines and direct it to a single output line 2 input lines, n selection lines and one output line n e.g.: 2-to-1-line multiplexer Fig. 4.24 Two-to-one-line multiplexer

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**4-to-1-line multiplexer**

Fig. 4.25 Four-to-one-line multiplexer

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**Note n-to- 2 decoder add the 2 input lines to each AND gate**

add the 2 input lines to each AND gate n OR(all AND gates) an enable input (an option)

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Fig. 4.26 Quadruple two-to-one-line multiplexer

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**Boolean function implementation**

MUX: a decoders an OR gate 2 -to-1 MUX can implement any Boolean function n of n input variable a better solution: implement any Boolean function of n+1 input variable n of these variables: the selection lines the remaining variable: the inputs

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**an example: F(A,B,C) = S(1,2,6,7)**

an example: F(A,B,C) = S(1,2,6,7) Fig. 4.27 Implementing a Boolean function with a multiplexer

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**procedure: assign an ordering sequence of the input variable**

assign an ordering sequence of the input variable the rightmost variable (D) will be used for the input lines assign the remaining n-1 variables to the selection Lines with construct the truth table lines w.r.t. their corresponding sequ consider a pair of consecutive minterms starting from m determine the input lines

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**Example: F(A, B, C, D) = S(1, 3, 4, 11, 12, 13, 14, 15) Fig. 4.28**

Implementing a four-input function with a multiplexer

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**Three-state gates A multiplexer can be constructed with three-state**

A multiplexer can be constructed with three-state gates Output state: 0, 1, and high-impedance (open ckts) Fig. 4.29 Graphic symbol for a three-state buffer

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**Example: Four-to-one-line multiplexer**

Fig. 4.30 Multiplexer with three-state gates

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