Download presentation

Presentation is loading. Please wait.

Published byCheyenne Warman Modified over 2 years ago

1
Chapter 4 Combinational Logic

2
Outline: 4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders Encoders Multiplexers. 2

3
4.1 Introduction Logic circuits for digit systems maybe combinational or sequential. A combinational circuit consists of logic gates whose outputs at any time are determend from only the presence combinations of inputs 2 A Sequential circuits contain memory elements with the logic gates the outputs are a function of the current inputs and the state of the memory elements the outputs also depend on past inputs. (chapter 5)

4
Outline: 4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders Encoders Multiplexers. 4

5
A combinational circuits 2possible combinations of input values n Combinational circuits Combinatixnal xoxic Circuit n input m output variables 4 Specific functions Adders, subtractors, comparators, decoders, encoders, andmultiplexers 4.2 Combinational Circuits

6
Outline: 4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders Encoders Multiplexers. 6

7
4.3 Analysis Procedure A combinational circuit make sure that it is combinational not sequential No feedback path or memory elements. derive its Boolean functions (truth table) designverification

8
Example: 6

9
F2= AB+AC+BC T1= A+B+C T2= ABC T3= F2’. T1 F1= T3+T2 = F2’. T1 +ABC = (AB+AC+BC)’.(A+B+C) +ABC = (A’+B’)(A’+C’)(B’+C’).(A+B+C) +ABC = (A’B’+A’B’C’+B’C’+A’C’). (A+B+C) +ABC = AB’C’+A’B’C+A’B’C+ABC 9

10
The truth table 8

11
Outline: 4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders Encoders Multiplexers. 11

12
4.4 Design Procedure The design procedure ofcombinational circuits From the scpecification of the circuit determine the required number of inputs and outputs. For each input and output variables assign a symbol Derivethe truth table Derive the simplified Boolan functions for each output as a function of the input variables Draw the logic diagram and verify the correctness of the design 9

13
Example: code conversion BCD to excess-3 code 11

14
The maps 12

15
The simplified functions z = D' y = CD +C'D‘ x = B'C + B‘D+BC'D' w = A+BC+BD z = D' y = CD +C'D'= CD + (C+D)' x = B'C +B'D+BC'D‘ = B'(C+D) +B(C+D)' w = A+B(C+D) 13 Another implementation

16
The logic diagram 14

17
Outline: 4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders Encoders Multiplexers. 17

18
4-5Binary Adder-Subtractor Half adder = 0 ; = 1 ; = 1 ;1+ 1 = 10 two input variables: x, y two output variables: C (carry), S (sum) truth table 15 S = x'y+xy‚ S=x y C = xy

19
17

20
20 Full-Adder A full adder is similar to a half adder, but includes a carry-in bit from lower stages. Like the half-adder, it computes a sum bit, S and a carry bit, C. For a carry-in (Z) of 0, it is the same as the half-adder: For a carry- in (Z) of 1: Z0000 X Y C S Z1111 X Y C S

21
Full-Adder : the arithmetic sum of three input bits three input bits x, y: two significant bits z: the carrybit from the previous lower significant bit Two outputbits: C, S 18

22
19

23
S = x'y'z+x'yz'+ xy'z'+xyz C = xy+ xz + yz S = z (x y) = z'(xy'+x‘y)+z(xy'+x'y)' = z‘xy'+z'x'y+z(xy+x‘y') = xy'z'+x'yz'+xyz+x'y'z C = z(xy'+x'y)+xy = xy'z+x'yz+ xy 20

24
Binary adder 21 Note: n bit adder requires n full adders

25
Binary subtractor A-B = A+(2’s complement of B) 4-bit Adder-subtractor using M as mode of operation M=0, A+B; M=1, A+B’+1 26

26
Overflow The storage is limited Overfow cases : 1.Add two positive numbers and obtain a negative number 2. Add two negative numbers and obtain a positivenumber V = 0, no overflow; V = 1, overflow 27 Example: Note: XOR is used to detect overflow.

27
Outline: 4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders Encoders Multiplexers. 27

28
4-6 Decimal Adder Add twoBCD's 9 inputs: two BCD's and one carry-in 5 outputs: one BCD and one carry-out A truth table with 2^9 entries the sum <= = 19 binary to BCD 28

29
BCD Adder: The truthTable 29

30
In BCD modifications are needed if the sum > 9 Must add 6 (0110) in case: C = 1 K = 1 Z8z4=1 Z = Z mo Ification when C=1 we add 6: mo d C = K +ZZ+ ZZ

31
Block diagram 31

32
Outline: 4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders Encoders Multiplexers. 32

33
4.7 Binary Multiplier Partial products –use AND operations with half adder. Note: A*B=1 only if A=B=1 Oherwise 0. fig Two-bit by two-bit binary multiplier. 33

34
4-bit by 3-bit binary multiplier Digital Circuits Fig Four-bit by three-bit binary multiplier. 34

35
Outline: 4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders Encoders Multiplexers. 35

36
4-9 Decoder We use here n-to-m decoder a binary code ofnbits = 2distinct information n n input variables;up to 2outputlines only on e output can be active (high) a t any time n 36 A decoder is a combinational circute that converts n-input lines to 2^n output lines.

37
An implementation Digital Circuits 38 Fig Three-to-eight-line decoder. 37

38
Demultiplexers a decoder with an enable input receive information in a single line and transmits itin one of2possible output lines n Fig Two-to-four-line decoder with enable input 38

39
Decoder Examples D 0 = m 0 = A 2 ’A 1 ’A 0 ’ D 1 = m 1 = A 2 ’A 1 ’A 0 …etc 3-to-8-Line Decoder: example: Binary-to-octal conversion.

40
Expansion two 3-to-8decoder: a 4-to-16 deocder a 5-to-32decoder? Fig 16 decoder constructed with two 3x8 decoders 40

41
Decoder Expansion - Example 2 Construct a 5-to-32-line decoder using four 3-8-line decoders with enable inputs and a 2-to-4-line decoder. D 0 – D 7 D 8 – D 15 D 16 – D 23 D 24 – D 31 A3A4A3A4 A0A1A2A0A1A2 2-4-line Decoder 3-8-line Decoder E E E E

42
Combination Logic Implementation each output = a minterm use a decoder andan external OR gate to implement any Boolean function of n input variables A full-adder S(x,y,z)= (1,2,4,7) C(x,y,z)= (3,5,6,7)C(x,y,z)= (3,5,6,7) Fig Implementation of a full adder with1decoder 42

43
two possible approachesusingdecoder OR(minterms of F): k inputs NOR(minterms of F'): 2 k inputs In general, it isnot apractical implementation n 43

44
Outline: 4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders Encoders Multiplexers. 44

45
4.10 Encoders The inverse function of decoder a decoder zDDDD y D DDD xDDDD The encoder can be implemented with three OR gates. 45

46
An implementation limitations illegal input: e.g. D 3636 The output = 111 (¹3 and ¹6) =Dx1 46

47
Priority Encoder resolve the ambiguity of illegal inputs only one of theinput is encoded D D 3 0 X: don't-careconditions V: valid output indicator has the highest priority has the lowest priority 47

48
■The maps for simplifying outputs x and y fig Maps for a priority encoder 48

49
■Implementation of priority Fig Four-input priority encoder xx yy DD DD V D DDD

50
Outline: 4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders Encoders Multiplexers. 50

51
4.11 Multiplexers select binary information from one of many input lines and direct itto a single output line 2input lines, n selection lines and oneoutput line e.g.: 2-to-1-line multiplexer n Fig Two-to-one-line multiplexer 51

52
4-to-1-line multiplexer Fig Four-to-one-line multiplexer 52

53
Note n-to- 2decoder n add the 2inputlines to eachAND gate OR(all AND gates) an enable input (anoption) n 53

54
Fig Quadruple two-to-one-line multiplexer 54

55
Boolean function implementation MUX: a decodersan OR gate 2 -to-1 MUX can implement any Boolean function of n input variable n n of these variables: the selection lines the remaining variable: the inputs a better solution: implement any Boolean function of n+1 input variable 55

56
an example: F(A,B,C) = (1,2,6,7) Fig Implementing a Boolean function with a multiplexer 56

57
Procedure: Assign anordering sequence of the inputvariable the rightmost variable(D) will be used forthe input lines assign the remaining n-1 variables to the selection 0 determine the input lines lines w.r.t. their corresponding sequ consider a pairof consecutive minterms starting from m 57 Lines with construct the truth table

58
Example: F(A, B, C, D) = (1, 3, 4, 11, 12,13, 14, 15) Fig Implementing a four-input functionwith a multiplexer 58

59
Three-state gates A multiplexer can be constructed with three-state gates Output state: 0, 1, and high-impedance (open ckts) Fig Graphic symbol for a three-state buffer 59

60
Example: Four-to-one-line multiplexer Fig Multiplexer with three-state gates 60

Similar presentations

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google