3 Enabling/Disabling Interrupt (1) °When an interrupt occurs, the Global Interrupt Enable I- bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable nested interrupts (risky!). The I-bit is set (one) when a Return from Interrupt instruction – RETI - is executed. °Instructions: SEI, CLI
4 Enabling/Disabling Interrupt (2) °The AT90S4414/8515 has two 8-bit Interrupt Mask control registers: GIMSK - General Interrupt Mask register to enable/disable external interrupts TIMSK - Timer/Counter Interrupt Mask register to enable/disable timer/counter interrupt
5 Remembering Interrupt °The AT90S4414/8515 has two 8-bit Interrupt Flag registers: GIFR - General Interrupt Flag register to remember external interrupts whenever it is being disabled TIFR - Timer/Counter Interrupt Flag register to remember timer/counter interrupt whenever it is being disabled
6 When Interrupt is Set - SEI °If the interrupting condition occurs, e.g. a change on the port bit, the processor pushes the actual program counter to the stack °After that, processing jumps to the predefined location, the interrupt vector, and executes the instructions there. Usually this is a JUMP instruction to the interrupt service routine somewhere in the code. The interrupt vector is a processor-specific location and depending from the hardware component and the condition that leads to the interrupt °The service routine must re-enable this flag after it is done with its job. The service routine can end with the command: RETI
9 Kerangka Program rjmp RESET rjmp EXT_INT0 RESET: ;init stack pointer ;init any ports used ;other init sei ;do things, main loop, etc EXT_INT0: ;do things reti
10 Contoh: Main Program.cseg.org INT0addr rjmpext_int0;External interrupt handler.org OVF0addr rjmptim0_ovf;Timer0 overflow handler main: Do some initializations rcalluart_init;Init UART sei;Enable interrupts idle: sbrsu_status,RDR;Wait for Character rjmpidle Do the work wait: sbrcu_status,TD;Wait until data is sent rjmpwait Wrap it up
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