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Effective Program Verification for Relaxed Memory Models Sebastian BurckhardtMadanlal Musuvathi Microsoft Research CAV, July 10, 2008.

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Presentation on theme: "Effective Program Verification for Relaxed Memory Models Sebastian BurckhardtMadanlal Musuvathi Microsoft Research CAV, July 10, 2008."— Presentation transcript:

1 Effective Program Verification for Relaxed Memory Models Sebastian BurckhardtMadanlal Musuvathi Microsoft Research CAV, July 10, 2008

2 Motivation: Memory Model Vulnerabilities Programmers do not always follow strict locking discipline in performance-critical code ◦ Ad-hoc synchronization with normal loads and stores or interlocked operations is faster ◦ Result: “benign” or “intentional” data races Such code can break on relaxed memory models ◦ Most multicore machines are not sequentially consistent ◦ Both compilers and actual hardware can contribute to effect Vulnerabilities are hard to find, reproduce, and analyze ◦ May require specific hardware configuration and schedule 2

3 C# Example volatile bool isIdling; volatile bool hasWork; //Consumer thread void BlockOnIdle(){ lock (condVariable){ isIdling = true; if (!hasWork) Monitor.Wait(condVariable); isIdling = false; } //Producer thread void NotifyPotentialWork(){ hasWork = true; if (isIdling) lock (condVariable) { Monitor.Pulse(condVariable); } 3

4 Key pieces of code on previous slide: On x86, hardware may perform store late Bug: Producer thread does not notice waiting Consumer, does not send signal Store ii, 1 Example: Store Buffer Vulnerability Store ii, 1 volatile int ii = 0; volatile int hw = 0; Load hw, 0 Load ii, 1 Store hw, 1 ConsumerProducer 0 0 4

5 Abstract View of Memory Models 5 Given a program P, a memory model Y defines the subset T P,Y  T of traces corresponding to some (partial or complete) execution of P on Y. T P, SC T T P, Y SC (sequential consistency) Is strongest memory model More executions may be possible on a relaxed memory model Y 5

6 Example: TSO 6 Under TSO, processors can buffer stores in FIFO queue. T P, SC T T P, TSO Trace corresponding to code on slide Store hw, Load ii, Store ii, Load hw, 0

7 Memory models are platform dependent & ridden with details We focus on TSO because it models store buffers, the most common relaxation In practice, TSO is almost the same as the x86 hardware model TSO PSO IA-32 Alpha RMO z6 SC IA-64 Why TSO? 7

8 Model Checking Programs on Relaxed Memory Models Covering all relaxed executions is challenging ◦ Highly nondeterministic (exposed to low-level hardware concurrency) ◦ Memory models are usually not finite-state ◦ Memory models are often a matter of negotiation (formal descriptions are the exception) State of the art has limited scalability ◦ Model checking using simplified operational models ◦ Bounded model checking using axiomatic models (CheckFence) 8

9 Memory Model Safety Observation: Programmer writes code for SC ◦ Resorts to {locks, fences, volatiles, interlocked operations} to maintain SC behavior where needed ◦ If program P exhibits non-SC behavior, it is most likely a bug Definition: A program P is Y-safe if T P,SC = T P,Y 9

10 Decomposed Program Verification on Relaxed Memory Models 1.Verify sequentially consistent executions (show that all executions in T P,SC are correct) 2.Verify memory model safety (show that T P,SC = T P,Y ) Can we do 1 and 2 at the same time? Yes. 10 T P, SC T T P, Y

11 Borderline Executions Def.: A borderline execution for P is an execution with a successor in T P,TSO - T P,SC Thm.: A program P is TSO -safe if and only if it has no borderline executions. T P,TSO T P,SC 11

12 Borderline Executions Def.: A borderline execution for P is an execution with a successor in T P,TSO - T P,SC Thm.: A program P is TSO -safe if and only if it has no borderline executions. T P,TSO T P,SC 12 We can verify / falsify this as a safety property of sequentially consistent executions!

13 Example: TSO Borderline Execution Store hw, Store ii, Load hw, Store hw, Load ii, Store ii, Load hw, Store hw, Load ii, Store ii, Load hw, 0 T P, SC T P, TSO Successor traces are traces with one more instruction.

14 Sober Tool Structure 14 Instrumented Program Borderline Monitor Stateless Model Checker (CHESS) Scheduler Enumerates Traces Event Stream (shared memory accesses, sync ops) Program output is always sound. Tool may not terminate exploration if # of executions is too large. Outputs: (1) P correct (2) P not TSO-safe (+cex) (3) P has SC-bug (+cex)

15 Define SC using  hb relation Trace = Set of Instructions (Vertices) with attributes ◦ [ processor ]. [ issue index ] [ operation ] [ address ], [ coherence index ] coh.index is the position of the value within the sequence of values written to the same location (i.e., “we replace each value with its sequence number”) Add edges: program order  p / conflict order  c Define happens-before order  hb = (  p   c ) Trace is sequentially consistent if and only if  hb is acyclic. 1.1 Store ii, Load hw, Load ii, Store hw, 1 This trace is SC: 1.1 Store ii, Load hw, Store hw, 1 This trace is not SC: 2.2 Load ii, 0 15

16  rhb Define TSO by Relaxing  hb Define relaxed happens-before order  rhb = (  p   c ) \ { (s,l) | s is store, l is load, and s  p l } Trace is possible on TSO if and only if (1)  rhb is acyclic (2) there do not exist s, l such that s  p l and l  c s This trace is TSO, but not SC: 2.1 Store hw, Load ii, 0  hb 1.1 Store ii, Load hw, Store hw, Load ii, Store ii, Load hw, Store hw, Load ii, Store ii, Load hw, 0 Thm.: Def. Is equivalent to operational TSO model (see Tech Report) 16

17 Borderline Monitor Implementation Receiving a stream of memory accesses: Record all stores to all locations. For each load L, check if there exists a reordering of L with prior stores to the same location such that (1)  hb has a cycle (2)  rhb is acyclic (3) there do not exist s, l such that s  p l and l  c s Implementation: use standard vector clock to compute  hb, and custom vector clock (twice the width) to compute  rhb 17

18 Equivalent Interleavings Typically, many different interleavings map to the same (Mazurkiewic) trace. By construction, our monitor is insensitive to the choice of interleaving ◦ Checks all  hb -equivalent ones simultaneously ◦ Makes it compatible with partial order reduction ◦ Improves probability of finding bugs 18

19 Results Good at finding bugs even if only a small number of schedules is explored ◦ Monitor checks all hb-equivalent interleavings ◦ Chess heuristic (iterative context bounding) seems to mix well Found expected store buffer vulnerabilities in standard examples (Dekker, Bakery) Detected 2 store buffer vulnerabilities in a production-level concurrency library. ◦ Overall code size ~ 33 kloc ◦ Used existing test harness written by product team (slightly adapted for use with CHESS) ◦ Bugs not previously known 19

20 20 programcontext# interleavingstimever. time [s] nameboundtotalborderline[s]SoBeRCHESS Fig. 1(b)∞104< 0.1< 0.2 dekker154< 0.1< 0.2 (2 threads,23623< crit-sec)318350< (loc 82)41,219124< ,472349< bakery011< 0.1< 0.2 (2 threads,12520< crit-sec) < (loc 122)312,4368,599< takequeue030n.a.< 0.3 (2 threads, ops) (loc 374)32,3181, ,1475, ,82117, Some Numbers

21 Conclusion With increasing use of multicores, more and more programs are likely to exhibit failures caused by the memory model. Such failures are hard to find by conventional means (code inspection, testing). Our combination of borderline monitor & stateless model checking makes it practical to detect memory model safety violations in a unit test environment. 21

22 Future Work Run on larger programs (runtime verification) Handle more memory models ◦ Which memory models guarantee borderline executions? Prove memory model safety of concurrent data type implementations Develop borderline monitors for other relaxed concurrent APIs ◦ Transactional memory ◦ Concurrency Libraries 22

23 How to check TSO safety? Given a program P, how to check T P,TSO = T P,SC ? Formulate TSO-safety as a safety property of the executions in T P,SC ! Then we can use conventional verification tools. 23

24 Reason About Successor Traces A successor is a trace with one more instruction opens door for non-temporal inductive reasoning! 1.1 Store ii, Store hw, Store ii, Store hw, Store ii, Store hw, Load ii, Store ii, Store hw, Load ii, 0


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