1. CMPE 421 Advanced Parallel Computer Architecture Pipeline datapath and Control

2. A Pipeline Datapath Revised: Single Cycle Datapath

3. An Instruction is divided into five pipelined stages. This means that five instructions will be in execution during any single cycle. For this reason we must separate the datapath into 5 pieces 1.Instruction Fetch 2.Instruction Decode/ Register Fetch 3.ALU Operation 4.Data Memory access 5.Write result into register Instruction Pipelining

4. Instructions and data move from left to right through these five stages as the complete the executuion However, there are two exceptions to this left to right flow of instructions – The write back stage in which the result is written back into the register file – Selecting the next value of the PC, choosing between the incremented PC and the branch address

5. LW instruction for pipelined Datapath To maintain proper time order, this stylized datapath breaks the register file into two logical parts: registers read during register fetch (ID) and registers written during write back (WB). This dual use is represented by drawing the unshaded left half of the register fi le using dashed lines in the ID stage, when it is not being written, and the unshaded right half in dashed lines in the WB stage, when it is not being read. As before, we assume the register fi le is written in the first half of the clock cycle and the register fi le is read during the second half.

6. The pipeline registers, in color, separate each pipeline stage. The pipeline register is used to pass any information needed in the next pipe stage They are labeled by the stages that they separate; for example, the first is labeled IF/ID because it separates the instruction fetch and instruction decode stages. The registers must be wide enough to store all the data corresponding to the lines that go through them. For example, the IF/ID register must be 64 bits wide, because it must hold both the 32-bit instruction fetched from memory and the incremented 32-bit PC address. We will expand these regis ters over the course of this chapter, but for now the other three pipeline registers contain 128, 97, and 64 bits, respectively LW instruction for pipelined Datapath

7. INSTRUCTION FETCH

8. Instruction Decode

9. Execution stage

10. Memory stage Data memory is read using the address in the EX/MEM pipeline registers, and the data is placed in the MEM/WB pipeline register. Next, data is read from the MEM/WB pipeline register and written into the register fi le in the middle of the datapath.

11. 11 A Bug! When the value read from memory is written back to the register file, the inputs to the register file (write register #) are from a different instruction! To fix the bug we need to save the part of the lw instruction (5 bits of it specify which register should get the value from memory).

12. The corrected pipeline datapath to properly handle the load instrucution The write register number now comes from the MEM/WB pipeline register along with the data. The register number is passed from the ID pipe stage until it reaches the MEM/WB pipeline register, adding fi ve more bits to the last three pipeline registers.

13. Five pipe stages of the store instruction

14. 14 Store Datapath: Stage 3

15. 15 Store Datapath: Stage 4

16. 16 Store Datapath: Stage 5

17. Pipeline Control Just as control was added to single cycle and multi-cycle implementations we must add it to the pipelined processor Unlike single cycle and multi-cycle, no instruction determines how all the control signals should be set Pipelining the datapath leaves the meaning of control lines unchanged Control signals are pipelined too (grouped by stage) The control unit is combinational again

18. Review: Single Cycle Control

20. Implementing Pipeline Control Use a Main Control unit to generate signals during RF/ID Stage – Control signals for EX (ExtOp, ALUSrc, …) used 1 cycle later – Control signals for Mem (MemWr, Branch) used 2 cycles later – Control signals for WB (MemtoReg, MemWr) used 3 cycles later

21. Assumptions for pipelining the control signals Initial design – motivated by single-cycle datapath control – use the same control signals Observe: – No separate write signal for the PC as it is written every cycle – No separate write signals for the pipeline registers (IF/ID, ID/EX, EX/MEM, MEM/WB), as they are written every cycle – No separate read signal for instruction memory as it is read every clock cycle – No separate read signal for register file as it is read every clock cycle Need to set control signals during each pipeline stage Since control signals are associated with components active during a single pipeline stage, can group control lines into five groups according to pipeline stage Will be modified by hazard detection unit!!

22. Implementing Pipeline Control

23. 23 Putting it All Together

24. 24 Comparison Clk Cycle 1 Multiple Cycle Implementation: IFRegEXMEMWB Cycle 2Cycle 3Cycle 4Cycle 5Cycle 6Cycle 7Cycle 8Cycle 9Cycle 10 LoadIFRegEXMEMWB IFRegEXMEM LoadStore Pipeline Implementation: IFRegEXMEMWBStore Clk Single Cycle Implementation: LoadStoreWaste IF R-type IFRegEXMEMWBR-type Cycle 1Cycle 2

25. 25 Got it?