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**Testability Measure What do we mean when we say a circuit is testable?**

Definition: A fault is testable if there exists a well-specified procedure to expose it within a reasonable cost. A circuit is testable if each and every fault in its specified fault set is testable. Literally, every well-specified man-made product is testable, as long as the specification is reasonable, i.e., so specified as to be used in a real environment. Why, then, is testability a growing concern, especially for VLSI circuits? Are people in this field defining testability differently? In fact, there is no precise definition for testability, and it will be impossible to give such a definition in general. It seems easier to define testability with respect to a fault. We say a fault is testable if there exists a well-specified procedure (e.g., test pattern generation, evaluation, and application) to expose it, and the procedure is implementable with a reasonable cost using current technologies. A testable fault is then one that can be tested with a reasonable effort. Note however that the definition is quite vague since it is not quantified; it is nothing more than an understanding among the practitioners in this field. Following the same mood, we may now say that a circuit is testable with respect to a fault set when each every fault in this set is testable.

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**Keys To Testability 1. Controllability 2. Observability**

3. Predictability Testability = Controllability + Observability + Predictability Design for testability (DFT) can be considered a class of design methodologies which put constraints on the design process to make test generation and diagnosis easier. Traditionally, the keys to testability are controllability and observability. The former refers to; how easy it is to control a certain wire of the DUT, i.e., to put a 0 or a 1 on the wire by PI assignment(s). The latter refers to how easy it is to observe a certain wire of the DUT, i.e., to deduce the signal value it caries from those of the POs. For sequential circuits, some have added predictability, which represents the ability to obtain known output values in response to given input stimuli. The factors affecting predictability include initializability, races, hazards, oscillations, etc. In this sense, we may formulate testability as follows: testability = controllability + observability + predictability.

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**Design for Testability**

To constrain the design to make test generation and diagnosis easier. In this chapter, we will describe testability measures which quantify the above concept. The measures are largely based on how hard the test patterns for the faults under consideration can be found. Note that predictability, although an important factor, is hard to quantify from only the netlist, so no well-known reliable technique has been developed for it. DFT, therefore, becomes techniques to add 'access' to the DUT with no or only a few extra i/o ports. It is receiving an increasing attention because test cost is becoming the most significant portion of the product development cost. In Fig. 6.1, it can be seen that without DFT, in general, a VLSI chip cannot be tested within a reasonable time interval, and the difficulty increases drastically as the chip size grows.

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**Testability (Controllability/Observability) Measures**

1. TMEAS [Stephenson & Grason, FTCS, 1976; DAC, 1979] 2. SCOAP [Goldstein, IEEE TCAS-26(9), 1979] 3. TESTSCREEN [Kovijanic 1979] 4. CAMELOT [Bennetts et al., 1980] 5. VICTOR [Ratiu et al., ITC, 1982] Some popular testability (controllability/observability) measures are listed below: 1. TMEAS [1, 2] 2. SCOAP [3] 3. TESTSCREEN [4, 5] 4. CAMELOT [6, 7] 5. VICTOR [8] 6. COMET [9] We will discuss some of them in detail.

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**Stephenson & Grason,s Approach**

Developed for register-transfer-level (RTL) circuits, but can also be applied at the gate level. The measures are normalized between 0 and 1 to reflect the ease of controlling and observing the internal nodes. This approach [1, 2] was developed for register-transfer-level (RTL) circuits, but can also be applied at the gate level. The measures are normalized between 0 and 1 to reflect the ease of controlling and observing the internal nodes. The approach is summarized as follows.

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**Stephenson & Grason,s Approach**

1. For each signal line s, we denote the controllability of s as CY(s) and the observability of s as OY(s). 2. The values for the CYs and the OYs of all the signal lines are derived by solving a system of simultaneous equations with the CYs and the OYs as unknowns. The expression used to calculate CY for each output zj is where CTF is the controllability transfer factor of the component.

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**Stephenson & Grason,s Approach**

Let Nj(0) and Nj(1) be the numbers of input combinations for which zj has value 0 and 1, respectively. Then 0 CTF 1. Each output controllability is assigned the same value.

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**Stephenson & Grason,s Approach**

The expression used to calculate OY for each input xi is where OTF is the observability transfer factor of the component.

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**Stephenson & Grason,s Approach**

Let NSi be the numbers of input combinations for which the change of xi results in a change of output. Then NSi also means the number of input combinations that can sensitize a path from xi to the output. The OTF measures the probability that a faulty value at any input will propagate to the outputs. 0 OTF 1 Each input observability is assigned the same value.

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**Stephenson & Grason,s Approach**

3. Fanouts: Let s be a fanout stem and k be the number of its branches. Then the CYs of each fanout branch is The observability of the fanout stem s is where bi are fanout branches of s. 4. Sequential components: Sequential components are modeled by adding feedback links around the components that represent internal states .

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**Goldstein,s Approach---SCOAP**

Sandia Controllability Observability Analysis Program. The measures reflect the difficulty of controlling and observing the internal nodes; higher numbers indicate more difficult to control or observe. The measures are, in a sense, minimum cost values for controlling and observing. The Sandia Controllability Observability Analysis Program (SCOAP) [3] is perhaps the most widely used approach. The measures reflect the difficulty of controlling and observing the internal nodes---higher numbers indicate more difficult to control or observe. The measures are, in a sense, minimum cost values for controlling and observing.

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**Goldstein,s Approach---SCOAP**

Combinational 1- and 0-controllabilities of Y = AND(A,B,C): CC1(Y) =CC1(A) + CC1(B) + CC1(C) + 1; CC0(Y) = min{CC0(A),CC0(B),CC0(C)} + 1. The result is incremented by 1 so that the number reflects (in part) the distance to the PIs. Working breadth-first from PIs toward POs, we calculate the CC of the output line of each logic cell as a function of the CCs of its input lines. To begin with, consider a three-input AND gate, Y = AND(A, B, C). The combinational 1-and 0-controllabilities of Y are CC1(Y) =CC1(A) + CC1(B) + CC1(C) + 1 and CC0(Y) = min{CC0(A),CC0(B),CC0(C)} + 1. Note that the result is incremented by 1 so that the number reflects (in part) the distance to the PIs. Working breadth-first from PIs toward POs, we can calculate the CCs of the output line of each logic cell as a function of the CCs of its input lines.

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**Goldstein,s Approach---SCOAP**

The sequential controllability provides an estimate of the number of time frames needed to provide a 0 or 1 at a particular node. For Y=XOR(A, B): CC0(Y) = min{CC0(A) +CC0(B), CC1(A) + CC1(B)} + 1 CC1(Y) = min{CC0(A) + CC1(B), CC1(A) + CC0(B)} + 1 SC0(Y) = min{SC0(A) + SC0(B), SC1(A) + SC1(B)} SC1(Y) = min{SC0(A) + SC1(B), SC1(A) + SC0(B)} When computing the sequential controllabilities through combinational circuits, the values are not incremented---no additional time frames needed.

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**Goldstein,s Approach---SCOAP**

When deriving equations for sequential circuits, SCs are incremented by 1, but CCs are not incremented. Positive edge-triggered DFF with active low reset: CC0(Q) = min{CC0(R), CC1(R) + CC0(D) + CC0(C) + CC1(C)} CC1(Q) = CC1(R) + CC1(D) + CC0(C) + CC1(C) SC0(Q) = min{SC0(R), SC1(R) + SC0(D) + SC0(C) + SC1(C)} + 1 SC1(Q) = SC1(R) + SC1(D) + SC0(C) + SC1(C) + 1

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**Goldstein,s Approach---SCOAP**

Observabilities: CO(P) = CO(N) + CC1(Q) + CC1(R) + 1 SO(P) = SO(N) + SC1(Q) + SC1(R) Positive edge-triggered DFF with active low reset: CO(R) = CO(Q) + CC1(Q) + CC0(R) SO(R) = SO(Q) + SC1(Q) + SC0(R) +1 To watch R, then have to watch Q and drive FF to ,1, and then reset it to ,0,.

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**Goldstein,s Approach---SCOAP**

May define testability as follows: T(l/o) = CC1(l) + CO(l) T(l/1) = CC0(l) + CO(l) Initial Condition Node PI PO IN CC CC SC SC CO SO 8 8 8 8 8 8

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**CAMELOT Controllability: CY(output) = CTF(output) x f(CYs(inputs));**

controllability transfer factor where N(0) and N(1) are the numbers of input combinations for which the output has value 0 and 1, respectively. The Computer-Aided MEasure for LOgic Testability (CAMELOT) [6, 7] was intended to be an improvement on TMEAS discussed above. The controllability values (denoted as CYs) are constrained to be in the range [0, 1], which represent the ease of controlling nodes. The expression to calculate an output CY of a component from its input CYs is CY(output) = CTF(output) x f(CYs(inputs)), where CTF is the controllability transfer factor of the component for the output concerned, and the function f combines the CYs of all the inputs to the component on which the particular output is dependent. A simple CTF is given by where N(0) and N(1) are the numbers of input combinations for which the output has value 0 and 1, respectively. Note the 1) 0 CTF 1, 2) CTF = 1 when N(0) = N(1), 3) CTF = 0 when N(0) =0 or N(1)= 0, and 4) each output has its own CTF (it has its own list of inputs that it depends on ).

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**CAMELOT CTF(NOT) = 1; CTF(NAND2) = 1/2;**

CTF(NAND3) = 1/4; CTF(ORn) =1/2n-1 CTF(XORn) = 1.

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**CAMELOT Q+ = [(JQ + KQ)C + QC]PR + P = JQCPR + KQCPR + QCPR + P**

Minterms in the final expression is 40; 24 invalid states; 16 common terms in this set of invalid states and the set of minterms derived above. N(1) = = 24, and N(0) = ( ) - N(1) = = 16. CTF = 1- (24-16)/40 = 0.8. By symmetry, the CTF for Q+ is also 0.8. Now consider the SN7476 JK-FF as shown. Q+ = [(JQ + KQ)C + QC]PR + P = JQCPR + KQCPR + QCPR + P A K-map can be used to calculate N(0) and N(1) for Q+. Alternatively, boolean expansion can be used iteratively to reintroduce missing variables to the product terms. The initial value of N(1) can be calculated by counting the minterms in the final expression, which is 40. However, we should take care of illegal or transient states: PRQ, PRQ, and PRQ, which represent 24 invalid states in total. There are 16 common terms in this set of invalid states and the set of minterms derived above for N(1), so the actual N(1) = = 24, and N(0) = (26 -24) - N(1) = = 16. Therefore, CTF = 1 - (24 -16)/40 = 0.8. By symmetry, the CTF for Q+ is also 0.8. Now, what is the function f ? In TMEAS, it is the arithmetic mean of all input CYs. Using the simple arithmetic mean for f : CY(Q+) = CTF(Q+) x {CY(P) + CY(J) + CY(K) + CY(C) + CY(R)}/5. If CY(C) = 1 but CY(J) =CY(K) = 0 because the state is to be fixed and CY(P) = CY(R) = 0 because the enable level is to be fixed, then CY(Q+) = 0.8 x 0.2 = 0.16, which is incorrect since Q+ cannot be changed in this case, i.e., CY(Q+) should be 0.

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**CY(output) = CTF(output) x f(CYs(input)), where**

CAMELOT CY(output) = CTF(output) x f(CYs(input)), where For unclocked circuits, the arithmetic mean is satisfactory for the function f. For clocked circuits, it should be modified. In general, CY(output) = CTF(output) x f(CYs(inputs)), where For the SN7476 JK-FF, CY(Q+) = CTF(Q+) x{CY(P) + CY(R) + CY(C)[CY(J) +CY(K)]}/4, which is 0 if CY(C) = 1 but CY(J) = CY(K) = CY(P) = CY(R) = 0. Now if CY(C) = CY(J) = CY(K) = 1 but CY(P) = CY(R) = 0, then CY(Q+) = CTF(Q+)/2. The division of 2 is unnecessary in this case, since full control of C, J, and K implies full control of Q+ in this case. We conclude that for FFs with P and R tied to a fixed value, they should be ignored when calculating the CYs.

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**CAMELOT Observability**

OY(at output) = OTF x OY(at input) x g(CYs(supporting inputs)), Where OTF is the observability transfer factor of the component for the input concerned. The observability values (denoted as OYs) are also constrained to be in the range [0, 1], which represent the ease of observing nodes. The expression to calculate an input OY of a component from its output OYs is OY(at output) = OTF x OY(at input) x g(CYs(supporting inputs)), where OTF is the observability transfer factor of the component for the input concerned. The OTF from input I of a component to its output O is denoted as OTF(I-O), which represents the ease of propagating a fault effect from I to O. Recall that in D-algorithm, each propagation D cube (PDC) identifies the sensitive path input, the fixed input combinations that support the sensitive path, and the sensitive path output. Each non-propagation D cube (NPDC), on the other hand, identifies the sensitive path input, the fixed input combinations that block the sensitive path, and the insensitive output. The total number of distinct, but unpolarized (considering D/E and D/E as the same) PDCs for an I-O pair quantifies the number of possible ways of fault-effect propagation, which is denoted as N(PDC:I-O). The total number of distinct, but unpolarized NPDCs for an I-O pair quantifies the number of possible ways of blocking the fault-effect propagation through the component, which is denoted as N(NPDC:I-O).

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CAMELOT where N(SP:I-O) is the total number of distinct sensitive paths from I to O, and N(IP:I-O) is the total number of insensi- tive paths. A simple OTF is then given by or, alternatively, where N(SP:I-O) is the total number of distinct sensitive paths from I to O, and N(IP:I-O) is the total number of insensitive paths. Note that transfer of sensitivity is assumed to occur from a single input to the relevent output, i.e., N(PDC:I-O) is actually the number of single-D PDCs for the component.

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**CAMELOT OTF(NOT) = 1; OTF(NAND2) = 1/2 for each input;**

OTF(NAND3) = 1/4 for each input (1 PDC & 3 NPDCs); OTF (XORn) = 1 for each input (0 NPDC).

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**CAMELOT Let OY(A-B) denote the observability of node A at node B, then**

OY(I-O) = OTF(I-O) x OY(I-I) x CY(av), where Now the function g is the average of the supporting inputs' CYs, calculated in the same way as the function f in the CY calculation. In general, let OY(A-B) denote the observability of node A at node B, then OY(I-O) = OTF(I-O) x OY(I-I) x CY(av), where In the case when node I is the clock node, then the clock CY is set to 1.

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CAMELOT Fanouts: For a reconvergent fanout, select the shortest I-O path which is to be sensitized (while others are blocked), which is more likely to result in a higher OY. For feedback paths, the strategy is similar to that for reconvergent fanouts with unequal path lengths (i.e., select the shortest path). The treatment of fanouts is the same as TMEAS, i.e., For a reconvergent fanout, select the shortest I-O path which is to be sensitized (while others are blocked), which is more likely to result in a higher OY. For feedback paths, the strategy is similar to that for reconvergent fanouts with unequal path lengths (i.e., select the shortest path).

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**Testability TY(node) = CY(node) x OY(node).**

CAMELOT Testability TY(node) = CY(node) x OY(node). A simple measure of testability (TY) can be derived from the product of CY and OY for a node: TY(node) = CY(node) x OY(node). The overall testability of a circuit is

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**CAMELOT CAMELOT() 1. input, check, and initialize circuit;**

2. calculate nodal CY values from PIs to POs; 3. calculate nodal OY values from POs to PIs; 4. calculate nodal TY values; 5. calculate TY and interpret the results; This is the overall procedure of CAMELOT.

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**Importance of Testability Measures**

They can guide the designers to improve the testability of their circuits. Test generation algorithms using heuristics usually apply some kind of testability measures to their heuristic operations (e.g., in making search decisions), which greatly speed up the test generation process. Testability figures are important in at least the following two respects. First, they can guide the designers to improve the testability of their circuits. After the testability of all internal nodes are analyzed, DFT techniques can be selected and applied in an efficient way (including Ad Hoc DFT techniques, full and partial scan, and BIST). The process can easily be automated. Second, test generation algorithms using heuristics usually apply some kind of testability measures to their heuristic operations (e.g., in making search decisions), which greatly speed up the test generation process.

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Bibliography (1) J. E. Stephenson and J. Grason, ,,A testability measure for register transfer level digital circuits,,, in Proc. Int. Symp. Fault tolerant Computing (FTCS), (Pittsburgh, PA), pp , June 1976. (2) J. Grason, ,,TMEAS-a testability measurement program,,, in Proc. IEEE/ACM Design Automation Conf. (DAC) , vol. 26, no. 9, pp , 1979. (3) L. H. Goldstein, ,,Controllability/observability analysis for digital circuits,,, IEEE Trans. Circuits and Systems, vol. 26, no. 9, pp , Sept (4) P. G. Kovijanic, ,,Testability analysis,,, in Proc. IEEE Semiconductor Test Conf., pp , 1979. (5) P. G. Kovijanic, ,,Computer-aided testability analysis,,, in Proc. IEEE Autotestcon, pp , 1979. (6) R. G. Bennetts, C. M. Maunder, and G. D. Robinson, ,,CAMELOT:a computer-aided measure for logic testability,,, IEE Proc. Pt. E, vol. 128, no. 5, pp , 1981. (7) R. G. Bennetts, Design of Testable logic Circuits. Reading, MA: Addison-Wesley, 1984.

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Bibliography (8) I. M. Ratiu, A. Sangiovanni-Vincentelli, and D. O. Pederson, ,,VICTOR: a fast VLSI testability analysis program,,, in Proc. Int. Test Conf. (ITC), (Philadelphia, PA), pp , Nov (9) W. C. Berg and R. C. Hess, ,,COMET : a testability analysis and design modification package,,, in Proc. Int. Test Conf. (ITC), (Philadelphia, PA), pp , Nov

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