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Technische universiteit eindhoven November 2000Ad Verschueren and Bart Theelen1 The Multi Micro Processor Eindhoven.

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Presentation on theme: "Technische universiteit eindhoven November 2000Ad Verschueren and Bart Theelen1 The Multi Micro Processor Eindhoven."— Presentation transcript:

1 technische universiteit eindhoven November 2000Ad Verschueren and Bart Theelen1 The Multi Micro Processor Eindhoven University of Technology Section of Information and Communication Systems

2 technische universiteit eindhoven November 2000Ad Verschueren and Bart Theelen2 Contents Introduction System architecture –O.S. in hardware: the ‘Task Control Unit’ Multi processing –Inter-MμP communication –External event handling Project status

3 technische universiteit eindhoven November 2000Ad Verschueren and Bart Theelen3 Introduction: what is it ? MμP = Scalable multi processor architecture implemented on a single chip for real-time (embedded) systems

4 technische universiteit eindhoven November 2000Ad Verschueren and Bart Theelen4 Features True (shared memory) multi processing –Scalable: number of processors is not fixed –Customisable: number and types of coprocessors varies On-chip operating system kernel –Priority based multitasking on multiprocessor –External event handling instead of interrupts –Transparent inter-MμP communication

5 technische universiteit eindhoven November 2000Ad Verschueren and Bart Theelen5 ‘Global Processing Unit’ = (shared) co-processor ‘Local Processing Unit’ = RISC core GPU m.y FPU GPU m.y FPU GPU 2.x LSU GPU 2.x LSU GPU m.1 FPU GPU m.1 FPU GPU 1 TCU GPU 1 TCU GPU 2.1 LSU GPU 2.1 LSU 1 LPU 1 LPU 2 LPU 2 LPU n LPU n LPU Function Switch Result Switch System architecture L1 I$ Control Space Event Inputs Inter-M  P Network L2 I$ Arbiter External Memory MultiPort D$ Register D$ ‘Task Control Unit’ = O.S. kernel in HW Task assignments

6 technische universiteit eindhoven November 2000Ad Verschueren and Bart Theelen6 TCU Network Management TCU Core The ‘Task Control Unit’ Executive Function Switch Function Rx Result Switch Result Tx LPUs Task Scheduler Task Scheduler Sorted Task List Sorted Task List Control Space Event Inputs Event Detect Link Network Task Admin Timers Switch MultiPort D$ Arbiter Resource Admin Resource Data Current idea: T9000 look-alike

7 technische universiteit eindhoven November 2000Ad Verschueren and Bart Theelen7 Multi processing LPU’s run multiple tasks in parallel Instruction set is ‘open ended’ –Only 1/16 of instruction space executed by LPU’s –Remainder split over up to 15 different GPU types –Each GPU type determines actual use of ‘opcode’ bits Function switch routes on GPU type –Non-blocking, task priority based, fair Result switch routes on task number –Non-blocking, FCFS

8 technische universiteit eindhoven November 2000Ad Verschueren and Bart Theelen8 Inter-MμP communication Each task and communication resource has a local # –‘Communication resource’ = semaphore, pipe or mailbox Each MμP has its own ‘network address’ –All elements addressed with network address and local # Communication is completely transparent –Every task can use every resource on the network –TCU shields network from tasks (no direct access) –To transfer large blocks of data, use a pipe !

9 technische universiteit eindhoven November 2000Ad Verschueren and Bart Theelen9 External event handling Interrupts and software O.S. kernel are absent here ! TCU checks ‘external event’ inputs for activity –Sends specified number of ‘units’ to specified counting semaphore upon detection of event input activity –Tasks can wait at semaphore for units generated by external events Semaphore to send units to (or wait at) need not be in the M  P where the task resides !

10 technische universiteit eindhoven November 2000Ad Verschueren and Bart Theelen10 Research Topics How to configure a MμP for an application domain? What limits configuring a MμP? What performance bottlenecks can be expected? What performance will a specific MμP configuration have? How should an efficient hardware OS kernel look like? How to incorporate (automatic) testability in a highly parametrisable development procedure? How can compilers cope with the flexibility in a MμP system? Ultimate goal: Tools for industry, which enable fast synthesis by automatically mapping specific performance requirements of an application domain onto an efficient MμP configuration

11 technische universiteit eindhoven November 2000Ad Verschueren and Bart Theelen11 Project status Currently, a project run by students ! –Modular by nature, easy to split the workload Partial designs of most elements present or coming –Instruction set of LPU and interfaces more or less fixed –Functionality of TCU under investigation Uses Interactive Design and Simulation System –Mixed level: RTL and algorithmic level blocks –Want to have complete algorithmic level model ASAP –From there to RTL and (automatically) VHDL/Verilog Questions ?


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