Presentation on theme: "THE SPARC ARCHITECTURE Presented By M. SHAHADAT HOSSAIN 041-122-044 NAIEEM TOURZO KHAN 041-079-044 SARDER FERDOUS SADIQUE 041-251-044."— Presentation transcript:
THE SPARC ARCHITECTURE Presented By M. SHAHADAT HOSSAIN NAIEEM TOURZO KHAN SARDER FERDOUS SADIQUE
INTRODUCTION SPARC stands for Scalable Processor ARChitecture. SPARC, formulated by SPARC Consortium and adopted by Sun Microsystems in 1985, is based on the RISC I & II designs engineered at the University of California at Berkeley from 1980 through SPARC is a CPU instruction set architecture (ISA), derived from a Reduced Instruction Set Architecture (RISC). The SPARC architecture is a public property in the sense that the semiconductor manufacturers are encouraged to produce their own implementation of the SPARC architecture upon a license from SPARC International.
THE OUTLINE THE SPARC PROCESSOR –The Modules Integer Unit (IU) Floating Point Unit (FPU) Co-Processor –Instructions –The Register Window Concept –Traps –Pipelining
THE SPARC PROCESSOR The SPARC processor is divided into three parts: –an Integer Unit (IU) –a Floating-Point Unit (FPU) –an optional Coprocessor (CP), each with its own registers. (32-bits wide). The SPARC processor can be in either of 2 modes: –Supervisor mode: The processor can execute any instruction, including the privileged instructions. –User mode: “User Application” programs will be executed in user mode.
THE MODULES Integer Unit (IU) Floating-Point Unit (FPU) CoProcessor (CP)
THE INTEGER UNIT (IU) Contains the general purpose registers and controls the overall operation of the processor. Executes the integer arithmetic instructions and computes memory addresses for loads and stores. Maintains the program counters and controls instruction execution for the FPU and the CP. May contain from 40 to 520, 32-bit general- purpose registers which corresponds to a group of 8 global registers and a circular stack of 16 registers, known as register windows. Integer Unit (IU)
THE FLOATING-POINT UNIT (FPU) The FPU has thirty-two 32-bit-wide registers. Double-precision values occupy an even- odd pair and extended-precision values occupy an aligned group of four registers. The FPU’s registers are accessed externally only via load and store instructions; there is no direct path between the IU and the FPU. Floating-Point Unit (FPU)
THE COPROCESSOR The coprocessor instructions mirror the floating-point instructions ; –Load/store coprocessor, –Branch on coprocessor condition codes, –Coprocessor operate (CPop). Coprocessor operate instructions can execute concurrently with integer instructions. The coprocessor unit has its own set of 32- bit registers. The actual configuration of registers is implementation-dependent. CoProcessor (CP)
INSTRUCTIONS Instructions fall into six basic categories –Load/Store –Arithmetic/Logical/Shift –Control Transfer –Read/Write Control Register –Floating-point Operate –Coprocessor Operate
THE REGISTER WINDOW CONCEPT The active window is identified by the 5-bit Current Window Pointer (CWP). Decrementing the CWP at procedure entry causes the next window to become active. Incrementing the CWP at procedure entry causes the previous window to become active. Register window overflow and underflow conditions are handled in software by a kernel trap handler. The Window Invalid Mask (WIM) can tag any window so that an overflow or underflow trap is generated whenever the CWP is about to point a tagged window.
THE SPARC’s CIRCULAR REGISTER WINDOWS The additional registers are hidden from view until you call a subroutine or other function. Where other processors would push parameters on a stack for the called routine to pop off, SPARC processors just "rotate" the register window to give the called routine a fresh set of registers. The old window and the new window overlap, so that some registers are shared.
TRAPS A trap is an unexpected procedural call. Traps –decrement the CWP to the next register window. –cause the hardware to write the trapped program counters and state of the registers into the local registers of the new window.
Single issue pipeline with 6 stages. 4 threads (group) supported per pipeline. Each thread has unique 1. Register state. 2. Instruction buffers. 3.Store buffers. The thread group shares: 1. L1 caches. 2. TLBs. 3. Execution units. 4. Pipeline resources SPARC Pipeline
CONCLUSION The SPARC architecture allows for high performance processor and system implementations at a variety of technology points The SPARC Architecture is presented. The basic modules of SPARC processor, namely the integer, floating point and coprocessor units are studied, in detail. The register window concept, which differs the SPARC processor from other processors is described.