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07/04/2013Bahman R. Alyaei1 Chapter 8 Digital Transmission Systems Part 3.

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Presentation on theme: "07/04/2013Bahman R. Alyaei1 Chapter 8 Digital Transmission Systems Part 3."— Presentation transcript:

1 07/04/2013Bahman R. Alyaei1 Chapter 8 Digital Transmission Systems Part 3

2 07/04/2013Bahman R. Alyaei2 14 Types of SDH Multiplexing SDH multiplexing combines low-speed digital signals such as 2, 34, and 140 Mbps signals with required Overhead to form a frame called STM-1. It also multiplexes ATM and ISDN signals into SDH frame. SDH is a Byte-Interleaving multiplexing system.

3 07/04/2013Bahman R. Alyaei3 Continue… SDH multiplexing includes two types: 1.Multiplexing lower- order SDH signals into higher-order signals. 2.Multiplexing low-rate tributary signals into SDH signal. The goods of different size is analogous to different data rates such as 140 Mbps, 34 Mbps, and 2 Mbps.

4 07/04/2013Bahman R. Alyaei4 14.1 Multiplexing 140 Mbps Signal into STM-1 First, the 140 Mbps PDH signal (E4) is adapted via bit rate justification into Container level 4 (C-4). The C-4 has 9 x 260 = 2340 bytes. The frame rate of C-4 is 8000 frames/Sec, every 125 μS. The rate of E4 signal after adaptation is 9 x 260 x 8 x 8000 = 149.760 Mbps

5 07/04/2013Bahman R. Alyaei5 Continue… A column of POH is added in front of every C-4 block in order to implement real-time monitoring over the 140 Mbps path signals. The resulting block is called Virtual Container level 4 (VC-4) with a rate of 9 x 261 x 8 x 8000 = 150.336 Mbps.

6 07/04/2013Bahman R. Alyaei6 C-4 260 9 139.264 Mbps149.760 Mbps 150.336 Mbps C-4 POH 9 261 POH 9 1

7 07/04/2013Bahman R. Alyaei7 150.336 Mbps 149.760 Mbps VC-4 9 261 C-4 POH 9 261 VC-4 9 261 =

8 07/04/2013Bahman R. Alyaei8 Continue… The VC-4 is loaded into the information Payload of the STM-1 frame. Location of the VC-4 within the Payload may float when it loads. Part of the VC-4 is transmitted in one STM-1 frame and another part in the next frame. This problem is solved by adding AU-PTR before the VC-4. It will indicate the start of the VC-4 in the Payload.

9 07/04/2013Bahman R. Alyaei9 Payload AU-PTR VC-4 Continue…

10 07/04/2013Bahman R. Alyaei10 Continue… The resulting block (VC-4 + AU-PTR) is called Administrative Unit level 4 (AU-4). It has the same basic structure of STM-1 frame (9 rows x 270 columns), but only without SOH. AU-4 = VC-4 + AU-PTR = STM-1 – SOH To complete the STM-1 frame, the SOH is added to AU-4.

11 07/04/2013Bahman R. Alyaei11 = VC-4 AU-PTR 270 9 9 AU-4 270 9 AU-4 SOH 3 5 9

12 07/04/2013Bahman R. Alyaei12

13 07/04/2013Bahman R. Alyaei13 Continue… The complete procedure of multiplexing 140 Mbps signal into STM-1 is as follow: 1.140 Mbps PDH signal adapted into container C-4. 2.Add POH to C-4 to form VC-4. 3.Add AU-PTR to VC-4 to form AU-4. 4.Add SOH to AU-4 to form STM-1.

14 07/04/2013Bahman R. Alyaei14 Continue… C-4 139.264Mbps C-4 PTR C-4 PTR SOH POH 155.52Mbps AU-4 VC-4 C4 STM-1

15 07/04/2013Bahman R. Alyaei15 14.2 Multiplexing 34 Mbps Signals into STM-1 Frame Three different 34 Mbps signals can be multiplexed into one STM-1 frame as follow: First, the 34 Mbps PDH signal is adapted via bit rate adaptation into container level 3 (C-3). The C-3 has 9 raw x 84 column = 756 Bytes. A column of POH is added in front of every C-3 block in order to implement real-time monitoring over the 34 Mbps signals The resulting block is called VC-3.

16 07/04/2013Bahman R. Alyaei16 C-3 84 9 34 Mbps 48.384 Mbps 48.96 Mbps C-3 POH 9 85 POH 9 1 34 Mbps

17 07/04/2013Bahman R. Alyaei17 C-3 POH 9 85 34 Mbps VC-3 85 9 48.96 Mbps VC-3 85 9 =

18 07/04/2013Bahman R. Alyaei18 Continue… Every VC-3 is assigned a 3-Byte Tributary Unit Pointer (TU-PTR) which allows VC-3 to float in the Payload. The area in which the VC-3 is allowed to float with the aid of TU-PTR is called Tributary Unit level 3 (TU-3). TU-PTR contains an address which indicates the start of the VC-3 in the TU-3. TU-3 frame structure is incomplete, therefore, 6-Bytes pseudo-random data (R) are stuffed to fill the gap of TU-3. The resulting block is called Tributary Unit Group 3 (TUG3).

19 07/04/2013Bahman R. Alyaei19 VC-3 85 9 TU-PTR 3 1 VC-3 86 9 TU-PTR 3

20 07/04/2013Bahman R. Alyaei20 VC-3 86 9 TU-PTR 3 TU-3 86 9 P T R 3 = TU-3 86 9 P T R 3 VC-3

21 07/04/2013Bahman R. Alyaei21 TU-3 86 9 P T R 3 R 6 1 TU-3 86 9 P T R 3 R 6 34 Mbps49.536 Mbps

22 07/04/2013Bahman R. Alyaei22 TU-3 86 9 P T R 3 R 6 TUG-3 86 9 = TUG-3 86 9 34 Mbps49.536 Mbps

23 07/04/2013Bahman R. Alyaei23 Continue… Three TUG-3 blocks are byte interleaved into a container C-4. Since the resulting structure has only 258 columns (3 x 86), two columns of stuffed bits are added to complete the C-4 structure. Finally, C-4 is multiplexed into STM-1 signal which is similar to multiplexing 140 Mbps signal into STM-1.

24 07/04/2013Bahman R. Alyaei24 TUG-3 #2 86 9 TUG-3 #3 86 9 TUG-3 #1 86 9....... 9 258

25 07/04/2013Bahman R. Alyaei25 TU-3 # 1 86 9 P T R 3 R 6 TU-3 # 2 86 9 P T R 3 R 6 TU-3 # 3 86 9 P T R 3 R 6..... 9 258

26 07/04/2013Bahman R. Alyaei26..... 9 258 Incomplete C-4 9 258

27 07/04/2013Bahman R. Alyaei27 Incomplete C-4 RR 258 9 2 C-4 260 9 C-4 260 9 34 Mbps 149.760 Mbps

28 07/04/2013Bahman R. Alyaei28 Continue… The complete procedure of multiplexing 34 Mbps signal into STM-1 is as follows: 1.The 34 Mbps signal is adapted into container C-3. 2.POH is added to C-4 to form VC-3. 3.TU-PTR is added to VC-3 to form TU-3. 4.Stuffing bits is added to TU-3 to fill the gap and form TUG-3.

29 07/04/2013Bahman R. Alyaei29 Continue… 5.By byte interleaving three TUG-3 blocks and adding two columns of stuffing bits, C-3 is formed. 6.A higher-order POH is added to V-4 to form VC-4. 7.AU-PTR is added to VC-4 to form AU-4. 8.Finally, SOH is added to AU-4 to form STM-1 signal.

30 07/04/2013Bahman R. Alyaei30 C-4VC-4 34 Mbps POH 155.52Mbps C-3 POH C-3 POH = VC-3 TU-PTR VC-3 TU-PTR TU-3 = TUG-3 = Incomplete C-4 TUG-3 Incomplete C-4 = C-4 = PTR VC-4 PTR AU-4 = SOH AU-4 SOH STM-1AU-4 SOH =

31 07/04/2013Bahman R. Alyaei31 C-4 VC-4 34 Mbps 155.52Mbps C-3VC-3TU-3 TUG-3 STM-1AU-4 + POH+TU-PTR +Stuffed bits 3 x TUG3 Interleave + Stuffed bits + HO-POH +AU-PTR+SOH

32 07/04/2013Bahman R. Alyaei32 14.3 Multiplexing 2 Mbps Signals into STM-1 Frame 63 E1 signals (2 Mbps) can be multiplexed into one STM-1 signal. First, the 2Mbps signal is adapted via bit rate adaptation into container level 1, order 2, C-12 Container C-12 accommodate 34 bytes. A Multiframe is formed by arranging Four C-12 basic frames side-by-side.

33 07/04/2013Bahman R. Alyaei33 Continue… Since the frequency of E1 is 8000 frames/sec. Therefore, the frame frequency of C-12 basic frame is also 8000 frames/sec. Hence, the frequency of the C-12 Multiframe is 2000 frames/sec. When a Multiframe multiplexed into STM-1 frame, they are placed in four successive STM-1 frames, instead of one single frame.

34 07/04/2013Bahman R. Alyaei34 Continue… The Multiframe is used for the convenience of rate adaptation. If E1 (2 Mbps) signals have standard rate of 2.048 Mbps, each C-12 will accommodate 256 bits (32 bytes) Payload (2.048 Mbps /8000 = 256 bits). However, when the rate of the E1 signals is not standard, the average bit number accommodated into each C-12 is not an integer. In this case, a Multiframe of four C-12 frames is used to accommodate signals.

35 07/04/2013Bahman R. Alyaei35 C-12 4 3 9 2 Mbps 3 C-12 125 μS 500 μS

36 07/04/2013Bahman R. Alyaei36 Continue… To monitor the performance of each 2 Mbps signal, a Lower-Order Path Overhead (LO-POH) with the size of one byte is added to the notch in the top-left corner of each C-12. Each Multiframe has four different LO-POH bytes: V5, J2, N2, and K4. The combination of a C-12 and a LO-POH byte is called Virtual Container level 1, order 2 (VC-12).

37 07/04/2013Bahman R. Alyaei37 C-12 K4N2J2V5 C-12 K4N2J2V5

38 07/04/2013Bahman R. Alyaei38 VC-12 C-12 K4N2J2V5 Equal

39 07/04/2013Bahman R. Alyaei39 Continue… Every Multiframe is assigned a four-byte Tributary Unit Pointer (TU-PTR) which allow it to float. There are four different pointer bytes: V1, V2, V3, and V4. The first two (V1, V2) contains an address indicating the start of the Multiframe. Then the information structure changes into Tributary Unit level 1, order 2 (TU-12) with 9 raws x 4 columns.

40 07/04/2013Bahman R. Alyaei40 VC-12 V4V3V2V1 VC-12 V4V3V2V1

41 07/04/2013Bahman R. Alyaei41 VC-12 V4V3V2V1 TU-12 Equal 9 4

42 07/04/2013Bahman R. Alyaei42 Continue… Three TU-12 frames from different Multiframes are byte interleaved to form a Tributary Unit Group 2 (TUG-2). In the next step, seven TUG-2 frames are byte interleaved in the same manner and add two columns of stuffed bits to form a TUG-3 structure. And finally, the procedure of multiplexing TUG-3 into STM-1 signal is the same as mentioned before.

43 07/04/2013Bahman R. Alyaei43 V5 V1 9 4 V5 V1 9 4 V5 V1 9 4 V5 V1 9 12

44 07/04/2013Bahman R. Alyaei44 V5 V1 9 12 9 TUG-2 Equal

45 07/04/2013Bahman R. Alyaei45 9 12 TUG-2 #1 TUG-2 # 2TUG-2 # 6TUG-2 # 7 …….. Incomplete TUG-3 9 84 Incomplete TUG-3 9 86 RR TUG-3 86 9 Byte interleaving RR 9 2 Equal

46 07/04/2013Bahman R. Alyaei46 Continue.. The complete procedure of multiplexing of 2 Mbps signal into STM-1 is as follow: 1.2 Mbps signal is adapted into C-12. 2.Add LO-POH to C-12 to form VC-12. 3.Add TU-PTR to VC-12 to form TU-12. 4.Multiplex three TU-12 frames to form TUG-2.

47 07/04/2013Bahman R. Alyaei47 Continue… 5.Multiplex seven TUG-2 frames and add two columns of stuffing bits to form TUG-3. 6.Multiplex three TUG-3 frames and add two columns of stuffing bits to form C-4. 7.Add HO-POH to C-4 to form VC-4. 8.Add AU-PTR to VC-4 to form AU-4. 9.Add SOH to AU-4 to form STM-1.

48 07/04/2013Bahman R. Alyaei48 C-12 VC-12TU-12VC-12TUG-2 Incomplete TUG-3RR RRTUG-3 RR 2 Mbps = = C-4 VC-4 POH C-4 = TU-12 TUG-2 = TUG-3 Incomplete C-4 POH AU-4 155.52Mbps STM-1

49 07/04/2013Bahman R. Alyaei49 C-12 VC-12 TU-12TUG-2 TUG-3 C-4 2 Mbps VC-4 AU-4 STM-1 + LO-POH+TU-PTR3 x TU-12 7 x TUG-2 + Stuffing bits 3 x TUG-3 + Stuffing bits+ HO-POH+AU-PTR +SOH 155.52Mbps

50 07/04/2013Bahman R. Alyaei50 SDH Multiplexing Structure STM-1 AU-4 TU-3 AUG-1 TUG-3 VC-3C-3 VC-4C-4 TU-12 VC-12C-12 TUG-2 ×1 ×3 ×1 ×7 ×3 139264 kbit/s 34368 kbit/s 2048 kbit/s Pointer processing Multiplexing Mapping Aligning AUG-4 AUG-16 AUG-64 STM-4 STM-16 STM-64 ×1 ×4

51 07/04/2013Bahman R. Alyaei51

52 07/04/2013Bahman R. Alyaei52 15 SDH Timing Compensation AU-PTR Basic SDH Overhead structure

53 07/04/2013Bahman R. Alyaei53 SDH Regenerator Section Overhead Layer

54 07/04/2013Bahman R. Alyaei54 SDH Multiplexer Section Overhead Layer

55 07/04/2013Bahman R. Alyaei55 SDH Multiplexer Section Overhead Layer

56 07/04/2013Bahman R. Alyaei56 SDH Path Overhead Layer

57 07/04/2013Bahman R. Alyaei57 SDH Path Overhead Layer

58 07/04/2013Bahman R. Alyaei58 Continue… The SDH signal was designed to be timing tolerant to support: 1.Plesiochronously timed, 2.Lower-rate signals, 3.Slight timing differences between synchronously timed NEs.

59 07/04/2013Bahman R. Alyaei59 Continue… Two mechanisms allow for robust timing compensation: 1.Variable bit justification of the lower-rate signal, 2.Pointer (PTR) adjustments between synchronous elements in the SDH network.

60 07/04/2013Bahman R. Alyaei60 Continue… PTR adjustments allow the VC-4 to float with respect to the SDH frame. Therefore, a single VC-4 Payload frame typically crosses the STM-1 frame boundary. The PTR is contained in the H1 and H2 bytes of the AU-PTR, and it is a count of the number of bytes the VC-4’s POH J1 byte is away from the H3 bytes, not including the SOH bytes. A valid VC-4 PTR can range from 0 to 782.

61 07/04/2013Bahman R. Alyaei61 PTR Bytes Designating the Start of the VC-4 POH

62 07/04/2013Bahman R. Alyaei62 Continue… When timing differences exist, dummy bytes can be inserted into the VC-4 without affecting the data. The PTR is adjusted to indicate where the real POH starts, the receiving end can effectively recover the Payload (i.e. ignore the dummy bytes). When justified bytes are used, they are always in the same location, regardless of where the POH starts.

63 07/04/2013Bahman R. Alyaei63 Continue… H3 bytes are called Negative Justification bytes and carry real Payload data for one frame during a PTR decrement. The three bytes following the last H3 byte in the VC-4 are called Positive Justification bytes and carry three dummy bytes of information for one frame during a PTR increment.

64 07/04/2013Bahman R. Alyaei64 1.f 1 = f 2 If there is no timing difference between two nodes, the incoming STM-1 Payload bit rate is identical to the transmitting source that drives the outgoing STM-1 frame rate. So, in this case, no PTR Adjustments are needed. Input frequency (Rate) Output frequency (Rate)

65 07/04/2013Bahman R. Alyaei65 Continue… 2.f 1 < f 2 There is a constant lack of Payload data to place into the outgoing SDH signal. To compensate, three dummy bytes are placed into the Positive stuff bytes and the data is moved to the right by three bytes, so the VC-4 PTR is incremented by one.

66 07/04/2013Bahman R. Alyaei66 Incrementing the Pointer Value

67 07/04/2013Bahman R. Alyaei67 Continue… 3.f 1 > f 2 Then, three extra VC-4 Payload bytes are stored into the Negative stuff bytes, H3, in the MSOH for one frame, while all the Payload data is moved to the left by three bytes and the PTR is decreased by one.

68 07/04/2013Bahman R. Alyaei68 Decrementing the Pointer Value

69 07/04/2013Bahman R. Alyaei69 Continue… The only equipment that can perform Path PTR Adjustments is MSTE (DXC and Access Multiplexer). Also, Path PTR Adjustments are not performed by PTE (i.e. Access Multiplexer, where the Payload data enters the SDH network) even though there are potential timing differences at these locations as well. The timing differences at PTEs are due to Plesiochronously-timed tributary signals and are corrected by traditional bit justification techniques.

70 07/04/2013Bahman R. Alyaei70 15 Multiplexing Revisited In SDH terms, multiplexing of non-SDH signals means adapting these signals to the structure and timing of an STM-1 signal, enabling these non-SDH signals to be transported inside the SDH network. The first step in the multiplexing of a non-SDH signal is mapping. Mapping of a non-SDH signal means increasing the frequency of the non-SDH signal to a pre- determined frequency and adding OH for each one of the non-SDH signals.

71 07/04/2013Bahman R. Alyaei71 15.1 Multiplexing 140 Mbps Revisited

72 07/04/2013Bahman R. Alyaei72 Continue… The first step is increasing the frequency of the 140 Mbps signal to the value of 149.76 Mbps, by using variable bit justification. The resulting structure is called a C-4. Next, add nine OH bytes to the C-4; this OH is called POH.

73 07/04/2013Bahman R. Alyaei73 Continue… These nine bytes are: J1, B3, C2, G1, F2, H4, Z4, and Z5, and the resulting structure is called a VC-4. The second step is the addition of a VC- 4 PTR. The resulting structure is called AU-4. Finally, MSOH and RSOH are added to the AU-4 to create the STM-1 signal.

74 07/04/2013Bahman R. Alyaei74 15.2 Multiplexing 34 Mbps Revisited

75 07/04/2013Bahman R. Alyaei75 Continue… The multiplexing of 34 Mbps signals into an STM-1 is similar to that of 140 Mbps signals. The major difference is that, because a VC-4 has a maximum Payload Capacity of 149.76 Mbps, it can transport three 34 Mbps signals. Each of the three transported 34 Mbps signals is assigned a separate set of POH identical to the POH used with the 140 Mbps signal.

76 07/04/2013Bahman R. Alyaei76 Continue… Another difference is that there are two levels of pointers: 1.One PTR for the VC-4, 2.One separate PTR for each of the three 34 Mbps signals. The synchronized 34 Mbps signals are called C-3s, and the structures created by adding the POH are called VC-3s.

77 07/04/2013Bahman R. Alyaei77 Continue… The three VC-3s along with their PTRs are called TU-3s. Once the three TU-3s have been created, they are combined to form the Payload of the VC-4.

78 07/04/2013Bahman R. Alyaei78 15.3 Multiplexing 2 Mbps Revisited

79 07/04/2013Bahman R. Alyaei79 Continue… The multiplexing of 2 Mbps signals into a STM-1 is similar to that of 34 Mbps signals. In this case, the STM-1 signal can transport 63 separate 2 Mbps signals. Therefore, as in the case of 34 Mbps signals, there are two levels of PTRs. Also, the POH assigned to each 2 Mbps signal is different from that used in 140 and 34 Mbps signals.

80 07/04/2013Bahman R. Alyaei80 Continue… The POH for a 2 Mbps signal consists of four bytes: V5, J2, Z6, and Z7. Unlike mapping of 140 and 34 Mbps signals, the types of 2 Mbps mappings are: 1.Plesiochronous, 2.Bit synchronous, 3.Byte synchronous.

81 07/04/2013Bahman R. Alyaei81 Continue… Each C-12 along with its POH is called VC-12. Each VC-12 along with its VC-12 PTR is called TU-12. Three byte interleaved TU-12s is called TUG-3. The Payload of the VC-4 is created by combining 7 TUG-3s with fixed justification.

82 07/04/2013Bahman R. Alyaei82 16 Disadvantages of SDH SDH has a lower bandwidth utilization ratio than PDH due to many OH bytes used for OAM. Direct adding and dropping of lower-rate signal is achieved using pointers which increases the complexity of the system. Software plays a large role in the system, as a result, SDH system is vulnerable to computer viruses.


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