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Instruction Set Issues: Branches (C) 2010 Robert Finch.

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Presentation on theme: "Instruction Set Issues: Branches (C) 2010 Robert Finch."— Presentation transcript:

1 Instruction Set Issues: Branches (C) 2010 Robert Finch

2 Branches Issue: Branch instructions need to encode a lot of information. Issue: Processsor performance often depends on branch performance. Branch instructions need to encode at least the following two pieces of information: –1) The reason the control flow is changing. –2) The new target address as a result. Target Addresses: In most cases the target address is encoded as a displacement from the current program counter address. This is called relative address branching. Relative branching has several desireable features. –1) it can be encoded using a few number of bits –2) it allows easy program relocation. There’s no need to modify the branch targets to relocate software.

3 Branches – Displacement Addressing Displacements have been found via research to almost always require less than 13 bits to encode. Displacements are often encoded with 16 or fewer bits in the instructions. Because there is a fair amount of information required for the typical branch instruction, relative displacement addressing is usually used. Relative displacement addressing is a compact form of storing the target address. A branch may require, an branch opcode, a branch condition, a test register field, and a target address. If other enhancements are included such as prediction, a branch instruction may contain five or six fields of information. Meaning: branch instructions are often packed with information. The complexities of flow controls and their usefulness often results in a significant portion of the instruction set (for example 25%) being dedicated to branching instructions.

4 Branches Absolute Addressing Although not often used because it requires a significant number of bits in the opcode, an alternate form of target address is the absolute address. In this case the address is represented directly in the instruction opcode. This means may be in use where the instruction opcode is sufficiently wide. For example with a 64 bit opcode, a 32 bit absolute address may be encoded, rather than a displacement amount. This approach has: –1) increased code readability (not significant usually) –2) decreased processor complexity, resulting in perhaps better performance.

5 Branches – Test Conditions There are two groups of conditional tests that can take place. General register based testing and flag based testing. A significant amount of information is contained in a general register itself. It’s often sufficient to know only whether the register is zero or negative, and this can be easily found directly from the register. The second common form of testing is flag testing. Status results from an operation are stored in a set of processor flags, for example carry and overflow. Then these special status flags can be tested.

6 Branches – Typical Encodings The reason for the branch is often encoded as a specific opcode but also is often encoded as a group of opcodes. Most processors have more than one branch cause. A couple of typical encoding means follows: opcode 6 Displacement 16 unused 5 1)the opcode itself contains the reason code. Often used when there are only a small number of conditional branches. For example: BEQZ / BNEZ. When testing only a general register’s status. opcode 6 Displacement 16 cond 4 unused 10 Ra 5 2) an additional field in the opcode identifies the status flags to be tested

7 Branches – Other Encodings. Wide opcode (48 bit opcode) absolute address branch opcode 6 Address 36 Ra 5

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