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CMPUT 680 - Compiler Design and Optimization1 CMPUT680 - Fall 2003 Topic B: Open Research Compiler José Nelson Amaral

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Presentation on theme: "CMPUT 680 - Compiler Design and Optimization1 CMPUT680 - Fall 2003 Topic B: Open Research Compiler José Nelson Amaral"— Presentation transcript:

1 CMPUT Compiler Design and Optimization1 CMPUT680 - Fall 2003 Topic B: Open Research Compiler José Nelson Amaral

2 CMPUT Compiler Design and Optimization2 Logical Compilation Model back end (be) linker (ld) WHIRL (.B/.I) obj (.o) a.out/.so Data Path Fork and Exec driver (sgicc/sgif90/sgiCC) front end + IPA (gfec/gfecc/mfef90) Src (.c/.C/.f)

3 CMPUT Compiler Design and Optimization3 Components of Pro64 Front end Interprocedural Analysis and Optimization Loop Nest Optimization and Parallelization Global Optimization Code Generation

4 CMPUT Compiler Design and Optimization4 Data Flow Relationship Between Modules Lower to High W. gfec gfecc f90 Local IPA Main IPA LNO Inliner WHIRL C WHIRL fortran Main opt Lower all lower I/O Lower Mid W CG.B.I -O 3.w2c.c -IPA.w2c.h.w2f.f -O 0 -O 2 /O 3 -phase: w=off Very high WHIRL High WHIRL Mid WHIRL Low WHIRL Take either path (only for f90)

5 CMPUT Compiler Design and Optimization5 Front Ends zC front end based on gcc zC++ front end based on g++ zFortran90/95 front end from MIPSpro

6 CMPUT Compiler Design and Optimization6 Intermediate Representation IR is called WHIRL zCommon interface between components zMultiple languages and multiple targets zSame IR, 5 levels of representation zContinuous lowering as compilation progresses zOptimization strategy tied to level

7 CMPUT Compiler Design and Optimization7 IPA Main Stage Analysis yalias analysis yarray section ycode layout Optimization (fully integrated) yinlining ycloning ydead function and variable elimination yconstant propagation

8 CMPUT Compiler Design and Optimization8 IPA Design Features zUser transparent zProvide info (e.g. alias analysis, procedure properties) smoothly to: yloop nest optimizer ymain optimizer ycode generator

9 CMPUT Compiler Design and Optimization9 Loop Nest Optimizer/Parallelizer zAll languages (including OpenMP) zLoop level dependence analysis zUniprocessor loop level transformations zAutomatic parallelization

10 CMPUT Compiler Design and Optimization10 Loop Level Transformations zBased on unified cost model zHeuristics integrated with software pipelining yLoop Fission yLoop Fusion yLoop Unroll and jam yLoop interchange yLoop Peeling yLoop Tiling yVector data prefetching

11 CMPUT Compiler Design and Optimization11 Parallelization zAutomatic Array privatization Doacross parallelization Array section analysis zDirective based OpenMP Integrated with automatic methods

12 CMPUT Compiler Design and Optimization12 Global Optimization Phase zUse only SSA as program representation zSSA is unifying technology zImplements all traditional global optimizations zEvery optimization preserves SSA form zCan reapply each optimization on as- needed basis

13 CMPUT Compiler Design and Optimization13 Pro64 Extensions to SSA zRepresenting aliases and indirect memory operations zIntegrated partial redundancy elimination (SSA PRE) zSupport for speculative code motion zRegister promotion via load and store placement

14 CMPUT Compiler Design and Optimization14 Feedback Used throughout the compiler zInstrumentation can be added at any stage zExplicit instrumentation data incorporated where inserted zInstrumentation data maintained and checked for consistency through program transformations.

15 CMPUT Compiler Design and Optimization15 Design for Debugability (DFD) and Testability (DFT) zDFD and DFT build-in from start zCan build with extra validity checks zSimple option specification used to: ySubstitute components known to be good yEnable/disable full components or specific optimizations yInvoke alternative heuristics yTrace individual phases


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