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CE AMPLIFIERS. The first step is to set up an operating or ‘Q’ point using a suitable bias circuit. We will, by way of introduction, use a so called load.

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Presentation on theme: "CE AMPLIFIERS. The first step is to set up an operating or ‘Q’ point using a suitable bias circuit. We will, by way of introduction, use a so called load."— Presentation transcript:

1 CE AMPLIFIERS

2 The first step is to set up an operating or ‘Q’ point using a suitable bias circuit. We will, by way of introduction, use a so called load line technique to see the interplay between the circuit and device constraints on voltage and current. This will provide a graphical analysis of amplifier behaviour.

3 CE AMPLIFIERS The following (simple) bias circuit uses a single resistor R B to fix the base current. It is not very good since the emitter/collector currents and hence the operating point (I C, V CE ) vary with β. This will be improved with stabilised bias circuits in due course.

4 CE AMPLIFIER, Simple bias RBRB RCRC GND +V CC ICIC IBIB

5 CE AMPLIFIER, Simple bias RBRB RCRC GND +V CC ICIC IBIB V CE V BE

6 CE AMPLIFIER, Simple bias To enable us to look at a particular numerical example we choose the supply voltage V CC = 5V and R C = 2.5 kΩ

7 CE AMPLIFIER, Simple bias RBRB 2.5 x 10 3 GND +5 ICIC

8 CE AMPLIFIER, Simple bias In later discussions an a.c. signal (and an additional load resistor) will be coupled to the d.c. circuit using coupling capacitors. The capacitor values are chosen so that their impedance (1/  C) is negligibly small (zero) at the a.c.(signal) frequency (or over the operating frequency range). A capacitor acts as a short circuit for d.c. and the d.c. bias circuit can be designed independently of the a.c. source and any ‘a.c. load’.

9 CE AMPLIFIER, Simple bias RBRB 2.5 x 10 3 GND +5 ICIC

10 CE AMPLIFIER, Simple bias From Kirchhoff, for the output, RCRC GND +V CC ICIC V CE

11 CE AMPLIFIER, Simple bias Numerically, x 10 3 I C -V CE =0 Or, rearranging, I C = (5 – V CE )/ (2.5 x 10 3 ) A plot of I C against V CE is a straight line with slope (– 1/ 2.5 x 10 3) It is called a load line and represents the variation of I C with V CE imposed by the circuit or load.

12 CE AMPLIFIER, Simple bias Another variation of I C with V CE is determined by the output characteristic.

13 CE AMPLIFIER, Simple bias Another variation of I C with V CE is determined by the output characteristic. The two relationships can be solved graphically for I C and V CE.

14 CE AMPLIFIER, Simple bias Thus we calculate three points on the load line I C = (5 – V CE )/ (2.5 x 10 3 ) as I C =0, V CE =5V I C = 1mA, V CE =2.5V V CE =0V, I C =5/2500 A = 2mA. To enable us to plot it on the output characteristic.

15 CE AMPLIFIER, Simple bias

16 The region along the load line includes all points between saturation and cut-off. The base current I B should be chosen to maximise the output voltage swing in the linear region. Bearing in mind that V CE (Sat)  0.2 V and V CE Max = 5V choose the operating (Q) point at I B = 10 μA.

17 CE AMPLIFIER, Simple bias ‘Operating’ or Q point set by d.c. bias.

18 CE AMPLIFIER, Simple bias From Kirchhoff, for the input, RBRB GND +V CC IBIB V BE

19 CE AMPLIFIER, Simple bias Remembering that V BE ~ 0.6 V (the base or input characteristic is that of a forward biased diode) we can find R B ~ 440 kΩ.

20 CE AMPLIFIER, Simple bias A a.c. signal is superimposed on top of the d.c. bias level. We are interested in the voltage and current gains for this a.c. component.

21 CE AMPLIFIER VSVS RSRS V CC GND V CE RLRL RBRB ICIC Signal outputSignal input RCRC

22 CE AMPLIFIER The Q (d.c. bias) value of V CE is about 2.5 V The maximum positive signal swing allowed is, therefore (5-2.5) V = 2.5 V (The total The maximum negative voltage swing allowed is (2.5 –0.2) V =2.3 V The maximum symmetric symmetric signal swing about the Q point is determined by the smaller of these, i.e. it is  2.3 V.

23 CE Amplifier To find the voltage and current gains using the load line method we must use the input and output characteristics.

24 CE Amplifier Diode dynamic resistance for signals = 1/slope at Q point! Defines transistor input impedance for signals Remember we selected I B = 10 μA

25 CE Amplifier From the input curve we estimate that as I B changes by  5μA about the bias level of 10μA then the corresponding change in V BE is about V. When i B =5μA, v BE = V; when i B =15μA, v BE =

26 CE Amplifier From the output characteristic curve we move up and down the load line to estimate that as I B changes by  5μA the corresponding change in V CE is about –2.5 V. (Note the negative sign!) When i B =5μA, v CE = 3.75V; when i B =15μA, v CE = 1.25V

27 CE Amplifier From the input curve we estimate that as I B changes by  5μA about the bias level of 10μA then the corresponding change in V BE is about V. When i B =5μA, v BE = V; when i B =15μA, v BE =

28 CE AMPLIFIER ‘Operating’ or Q point set by d.c. bias.

29 CE Amplifier The CE small signal (a.c.) voltage gain is

30 CE Amplifier From the output characteristic curve we also see that as we move up and down the load line a change in I B of  5μA produces a corresponding change in I C of  5mA. The a.c. signal current gain is 100. This is consistent with the ideal characteristic uniform line spacing, i.e. β = 100 = constant.

31 CE AMPLIFIER ‘Operating’ or Q point set by d.c. bias.

32 Ideal CE Amplifier Summary The CE voltage and current gains are high The voltage gain is negative, i.e. the output signal is inverted. The d.c. bias current sets the signal input impedance of the transistor through the dynamic resistance. I C = β I B ; i C = β i B.

33 Ideal CE Amplifier Summary Two of these statements: The d.c. bias current sets the signal input impedance of the transistor through the dynamic resistance. I C = β I B ; i C = β i B. will be used to derive our simplified small signal equivalent circuit of the BJT. (It is simplified because it is based on ideal BJTs)

34 Additional a.c. Load Suppose an a.c. coupled load R L = 2.5 kΩ is added vinvin GND v out RLRL RCRC C V CC

35 Additional a.c. Load The ‘battery’ supplying the d.c. supply V CC has negligible impedance compared to the other resistors, in particular R C. It therefore presents an effective ‘short-circuit’ for a.c. signals. The effective a.c. load is the parallel combination of R C and R L. (From the collector C we can go through R C or R L to ground)

36 Additional a.c. load RCRC GND RLRL a.c. short via d.c. supply iCiC

37 RCRC GND RLRL iCiC Additional a.c. load v ce

38 Additional a.c. Load We now need to construct an a.c. load line on the output characteristic. This goes through the operating point Q and has slope This is hard to draw!

39 Additional a.c. Load a.c. load line, drawn with required slope through Q point.

40 Additional a.c. Load The available voltage swing and the voltage gain are calculated using the a.c. loadline. Symmetric swing reduced to about  1.25 V Voltage gain reduced to about –50.

41 Stabilised Bias Circuits These seek to fix the emitter current independently of BJT parameter variations, principally in β. This is best achieved by introducing an emitter resistance and setting the base voltage via a resistor network (R 1, R 2 ) which acts as a potential divider (provided I B can be assumed small)

42 Stabilised Bias Circuit VSVS RSRS V CC GND v out RCRC R1R1 R2R2 RERE Bias bit of the circuit, a.c. source and load capacitor coupled. R E is capacitor by- passed (shorted) for a.c. signals

43 Stabilised Bias Circuit See handout for a detailed analysis of this bias circuit We will also look at a worked example of a transistor amplifier based on such a stabilised bias circuit once we have established an a.c. equivalent circuit for the transistor.

44 Stabilised Bias Circuit Finally we give another circuit which provides bias stability using negative feedback from the collector voltage. +V CC GND D.C collector voltage V C RCRC RBRB V BE =0.6 V IBIB ICIC

45 Stabilised Bias Circuit +V CC GND D.C collector voltage V C RCRC RBRB V BE =0.6 V IBIB I RC ICIC

46 Stabilised Bias Circuit +V CC GND D.C collector voltage V C RCRC RBRB V BE =0.6 V IBIB I RC ICIC

47 Stabilised Bias Circuit For example, increasing , increases I C which lowers the collector voltage V C and hence and I B and I C +V CC GND D.C collector voltage V C RCRC RBRB V BE =0.6 V IBIB ICIC


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