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**Operational Amplifier Stability**

Collin Wells Texas Instruments HPA Linear Applications 2/22/2012

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**The Culprits!!! Capacitive Loads! High Feedback Network Impedance!**

Reference Buffers! Cable/Shield Drive! MOSFET Gate Drive! High Feedback Network Impedance! High-Source Impedance or Low-Power Circuits! Transimpedance Amplifiers! Attenuators! Let’s first introduce the main culprits when we notice our step response creates an oscillator! The first most common culprit is the capacitive load. I think we see this issue more than any other that we encounter. Capacitive Load circuits can be obvious or not here are some examples: Reference Buffers Cable/Shield Drive MOSFET Gate Drive “Filters” The second are circuits with high feedback resistance usually a result of efforts to lower the power dissipation or lower the loading of a high impedance sensor in an inverting configuration. Here are some examples: High Source Impedance Sensors Low-power circuits Attenuators Transimpedance amps!!

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**Just Plain Trouble!! Inverting Input Filter?? Oscillator**

Output Filter?? Oscillator These two circuits are basically always trouble, watch out for them!

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**Recognize Amplifier Stability Issues on the Bench**

Required Tools: Oscilloscope Step Generator Other Useful Tools: Gain / Phase Analyzer Network / Spectrum Analyzer If you’re in a situation in a lab where a stability issue could explain the results a circuit is producing or are trying to verify that your circuit is stable. Then the only real tool that’s required to debug the circuit is an oscilloscope! A step generator will be very useful but you may be able to use the standard input to your system to test the results. Other tools that can be used are gain/phase analyzers to look for AC peaking in the frequency response or a network/spectrum analyzer to see if there are any unexpected frequencies in the response due to oscillations or to look at the distortion.

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**Recognize Amplifier Stability Issues**

Oscilloscope - Transient Domain Analysis: Oscillations or Ringing Overshoots Unstable DC Voltages High Distortion If you observe anything that looks like these slides then your circuit probably has an oscilation issue. You may notice that the circuit is just outright oscillating. The oscillations may come and go over temperature and loading! If the circuit is mildly unstable it may not oscillate but if a step response is applied it may overshoot and ring heavily. This will affect the settling time performance of the circuit and may cause erroneous readings if the circuit does not settle before the measurement is made.

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**Recognize Amplifier Stability Issues**

Gain / Phase Analyzer - Frequency Domain: Peaking, Unexpected Gains, Rapid Phase Shifts Looking at the AC transfer function will show whether the circuit produces the expected response or if it has some unexpected peaking or rapid phase shifts. Either of these situations are signs of instability.

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**What causes amplifier stability issues???**

So what is the issue at the root of all stability issues?

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**Cause of Amplifier Stability Issues**

Too much delay in the feedback network There is too much delay between the output and the fed-back input of the circuit. This prevents the amplifier from being able to sense changes in the output quick enough to react to them and as a result the circuit begins to uncontrollably oscillate back and forth.

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**Cause of Amplifier Stability Issues**

Example circuit with too much delay in the feedback network So here is a practical circuit representation of delay in the feedback of an amplifier. A few RC elements are sufficient to delay the feedback enough to cause an uncontrollable oscillation. This seems a little unreasonable though right? Who would ever design a circuit that looked like that?

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**Cause of Amplifier Stability Issues**

Real circuit translation of too much delay in the feedback network Well what if we re-draw the previous circuit to look like a non-inverting amplifier driving a heavy capacitive load with a stray capacitance combining with the amplifier’s input capacitance? There are still two RC delays in this circuit, one from Ro and Cload and one from R1 and Cin+Cstray

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**Cause of Amplifier Stability Issues**

Same results as the example circuit Retesting shows that the results are the same as the “unrealistic” example circuit.

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**How do we determine if our system has too much delay??**

So how do we measure and determine if the feedback network of our amplifier has too much delay?

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**Phase Margin Phase Margin is a measure of the “delay” in the loop**

Open-Loop The Phase Margin of an amplifier circuit dictates how much phase shift is left in the circuit before the phase shift equals 180 degrees. The LoopGain (AOL*B) Phase shift is a measure of how many degrees of phase shift there are from the output to the input of an amplifier. Phase Margin is a measure of the difference in degrees between the Loopgain phase shift and 180 degrees when the LoopGain Magnitude equals 0dB. A phase shift of 180 degrees or more is completely unstable and will likely oscillate uncontrollably. So typically it is desired that the LoopGain have a phase shift less than 135 degrees which yields a phase margin of 45 degrees or more. Having at least 45 degrees of phase margin allows for a good safety margin due to standard shifts in AOL over process variations, temperature, and loading, or component value shifts, or any other occurrences that could cause the phase margin to decrease from the standard values.

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**Damping Ratio vs. Phase Margin**

Phase margin is not very easy to measure in the lab because it requires the user to break the loop with some type of transformer that will allow the tester to inject a small signal into the loop and observe the gain at different parts of the loop. Luckily as mentioned earlier all we need is an oscilloscope and a step generator!! If we can measure the overshoot of the circuit with a small signal input that produces an output change of between 50mV – 500mV then we can measure the overshoot and relate it back to phase margin using the chart listed. From: Dorf, Richard C. Modern Control Systems. Addison-Wesley Publishing Company. Reading, Massachusetts. Third Edition, 1981.

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**Small-Signal Overshoot vs. Damping Ratio**

Phase Margin Overshoot 90° 80° 2% 70° 5% 60° 10% 50° 16% 40° 25% 30° 37% 20° 53% 10° 73% Phase margin is not very easy to measure in the lab because it requires the user to break the loop with some type of transformer that will allow the tester to inject a small signal into the loop and observe the gain at different parts of the loop. Luckily as mentioned earlier all we need is an oscilloscope and a step generator!! If we can measure the overshoot of the circuit with a small signal input that produces an output change of between 50mV – 500mV then we can measure the overshoot and relate it back to phase margin using the chart listed. From: Dorf, Richard C. Modern Control Systems. Addison-Wesley Publishing Company. Reading, Massachusetts. Third Edition, 1981.

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**AC Peaking vs. Damping Ratio**

Phase Margin AC Peaking @Wn 90° -7dB 80° -5dB 70° -4dB 60° -1dB 50° +1dB 40° +3dB 30° +6dB 20° +9dB 10° +14dB Similar to the overshoot measurement, an AC peaking measurement can be converted back to phase margin by comparing the AC peaking to the damping ratio which can be converted back to phase margin as well. From: Dorf, Richard C. Modern Control Systems. Addison-Wesley Publishing Company. Reading, Massachusetts. Third Edition, 1981.

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Rate of Closure Rate of Closure: Rate at which 1/Beta and AOL intersect ROC = Slope(1/Beta) – Slope(AOL) ROC = 0dB/decade – (-20dB/decade) = 20dB/decade Phase margin only shows the final result while rate of closure will help the designer determine if the issues lies within the feedback and 1/B or in the loaded AOL curve.

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**Rate of Closure and Phase Margin**

Relationship between the AOL and 1/Beta rate of closure and Loop-Gain (AOL*B) phase margin In a system where the rate of closure is 20dB/decade we can infer that there is at least 45degrees of phase margin remaining. This is because we can assume every amplifier circuit begins with 180 degrees of phase margin and 90 degrees is removed with the dominant low-frequency pole. Therefore if we have 90 degrees remaining for until the loop is closed and we do not want to give up more than another 45 degrees then we need to make sure that there is not a pole in AOL or zero in 1/B closer than 1 decade to the ROC. At one decade away the pole or zero that causes the phase margin to decrease will only cause an additional 45 degrees of phase shift. Using the same logic if there is a known reaction in the system that causes the phase margin to decrease by an additional 90 degrees, such as a capacitive load interacting with the Zo of the amplifier, then we must place a compensation at least 1 decade before the ROC so we can ensure the phase is boosted at least back to 45 degrees by the time the loop closes.

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**Understanding Amplifier Stability Issues**

So a pole in AOL or a zero in 1/Beta inside the loop will decrease AOL*B Phase!! So if we have a pole in the AOL plot or a zero in the 1/Beta plot or some other combination of the two can cause the ROC to be >20dB/decade and the system will be unstable.

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**Understanding Amplifier Stability Issues**

AOL Pole 1/Beta Zero So if we have a pole in the AOL plot or a zero in the 1/Beta plot or some other combination of the two can cause the ROC to be >20dB/decade and the system will be unstable.

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**Both circuits have a NOISE GAIN (NG) of 2.**

Understanding Noise Gain vs. Signal Gain Inverting Gain, G = -1 Non-Inverting Gain, G = 2 All stability analysis is performed based on the “Noise Gain” of the circuit which is the gain seen by the non-inverting terminal of the amplifier. This is because noise sources are always modeled at the non-inverting input and if the non-inverting input sees an unstable system then the noise will cause the amplifier to oscillate uncontrollably. So the circuit on the left has a signal gain of -1V/V. The same circuit when the input is applied to the non-inverting terminal has a signal gain of 2V/V. Since noise gain is always taken from the non-inverting terminal both of these circuits have a noise gain of 2V/V. NG = 1 + ΙGΙ = 2 NG = G = 2 Both circuits have a NOISE GAIN (NG) of 2.

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**Noise Gain Noise Gain vs. Signal Gain Gain of -0.1V/V, Is it Stable?**

Inverting Gain, G = -0.1 Noise Gain, NG = 1.1 This is just a quick slide to debunk a common myth that a circuit with a gain less than unity is unstable. As long as the amplifier is unity-gain stable then since the noise gain is always 1+X then no matter how small the attenuation factor is, the noise gain will always be greater than 1. Ex: /100 = 1.01. If it’s unity-gain stable then it’s stable as an inverting attenuator!!!

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**Testing for Rate of Closure in SPICE**

Break the feedback loop and inject a small AC signal Short out the input source Break the loop with L1 at the inverting input To determine the open-loop parameters of their closed-loop system the loop must be broken! Break the loop by inserting an extremely large inductance which will be a short at DC and will open the circuit up for all AC frequencies. Then inject an AC signal into the loop through an extremely large capacitor that will be an open at DC and a short at all AC frequencies. Inject an AC stimulus through C1

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Breaking the Loop DC AC To determine the open-loop parameters of their closed-loop system the loop must be broken! Break the loop by inserting an extremely large inductance which will be a short at DC and will open the circuit up for all AC frequencies. Then inject an AC signal into the loop through an extremely large capacitor that will be an open at DC and a short at all AC frequencies.

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**Plotting AOL, 1/Beta, and Loop Gain**

AOL = Vo/Vin 1/Beta = Vo/Vfb AOL*B = Vfb/Vin With AOL, 1/Beta, and AOL*B we can determine the rate of closure and phase margin of this system. In this case the ROC is 20dB/decade and the PM is 88 degrees. This is a very stable system. Note 1/Beta = 6dB or 2V/V. The circuit we are analyzing was an inverting amplifier with a gain of -1V/V. However, the noise gain is taken from the positive input so the 1/Beta is 1+ |G| = 2V/V = 6dB.

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Capacitive Loads

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**Capacitive Loads Unity Gain Buffer Circuits Circuits with Gain**

As mentioned previously, the most common stability issues that we encounter involve capacitive loads. There are several ways to solve issues with capacitive loads, but the if the circuit must remain a unity-gain buffer then the options are limited. Therefore this section will be divided into two parts, unity-gain buffer circuits and circuits with gain.

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**Capacitive Loads – Unity Gain Buffers - Results**

Determine the issue: Pole in AOL!! ROC = 40dB/decade!! Phase Margin 0!! NG = 1V/V = 0dB Unity-gain buffers are actually the most difficult circuits to compensate because the loopgain is not reduced and is open to the full frequency range of the AOL. Therefore a pole in AOL or zero in 1/B at higher frequencies may affect a unity-gain circuit where it would not have affected a circuit with a higher gain. Breaking the loop shows us that an interaction with the capacitive load is causing a pole in the AOL block that is causing our 1/Beta with a slope of 0dB/decade to intersect the AOL with a slope of -40dB/decade at a rate of closure of 40dB/decade. As explained previously this tells us that the phase margin will be reduced by the pole in the loop. Checking the phase margin shows that the pole was more than a decade from the frequency of intersection resulting in a phase margin of 0degrees. This explains why we observed the heavy overshoots and ringing shown on the previous slide.

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**Capacitive Loads – Unity Gain Buffers - Theory**

Looking at a simplified model of the OPA627 we can see that there is a non-zero open-loop output impedance of roughly 50 ohms. Quick reminder that the amplifier is open-loop for all AC frequencies as shown with the open inductor and closed capacitor. Since the loop is open the output impedance and capacitive load appear as a load on the AOL block which can be modeled as shown in the image on the right. Looks like a very familiar RC low-pass filter now, huh?

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**Capacitive Loads – Unity Gain Buffers - Theory**

A quick analysis of the circuit shows that the transfer function from AOL to the actual amplifier output now is now comprised of a single-pole response with the pole location at 1/(2*pi*Ro*Cload) Plotting this shows a reduction in the magnitude response with a -3dB point at the pole location. The phase response shows that the phase begins to decrease a decade before the pole frequency and continues to decrease until a decade after the pole totaling a 90 degree phase shift.

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**Capacitive Loads – Unity Gain Buffers - Theory**

AOL AOL Load X So to look at the effect on the final AOL graphically, we have the initial AOL of the OPA627 on the left multiplied by the response of the AOL output load. A multiplication is an addition in the log-domain which is how we obtain the final response shown in the bottom circuit. The pole begins reducing the AOL at the pole frequency and the phase is shifted to basically 0 degrees for a unity-gain system. Loaded AOL =

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**Stabilize Capacitive Loads – Unity Gain Buffers**

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Stability Options Unity-Gain circuits can only be stabilized by modifying the AOL load

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Method 1: Riso The second method that we will look at uses an isolation resistor again to break capacitive load from the amplifier output. A high-frequency feedback is taken directly around the amplifier making a buffer driving Riso+Cload at high frequencies. The DC loop is closed on the other side of the isolation resistor so there isn’t a DC drop even with a load.

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Method 1: Riso - Results Theory: Adds a zero to the Loaded AOL response to cancel the pole Unity-gain buffers are actually the most difficult circuits to compensate because the loopgain is not reduced and is open to the full frequency range of the AOL. Therefore a pole in AOL or zero in 1/B at higher frequencies may affect a unity-gain circuit where it would not have affected a circuit with a higher gain. Breaking the loop shows us that an interaction with the capacitive load is causing a pole in the AOL block that is causing our 1/Beta with a slope of 0dB/decade to intersect the AOL with a slope of -40dB/decade at a rate of closure of 40dB/decade. As explained previously this tells us that the phase margin will be reduced by the pole in the loop. Checking the phase margin shows that the pole was more than a decade from the frequency of intersection resulting in a phase margin of 0degrees. This explains why we observed the heavy overshoots and ringing shown on the previous slide.

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Method 1: Riso - Results When to use: Works well when DC accuracy is not important, or when loads are very light The first method we will look at to stabilize the capacitive load is to add a series resistor or “isolation resistor” , Riso, between the amplifier output and the capacitive load. This will add a zero to cancel the pole in the Loaded AOL.

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Method 1: Riso - Theory Looking at a simplified model of the OPA627 we can see that there is a non-zero open-loop output impedance of roughly 50 ohms. Quick reminder that the amplifier is open-loop for all AC frequencies as shown with the open inductor and closed capacitor. Since the loop is open the output impedance and capacitive load appear as a load on the AOL block which can be modeled as shown in the image on the right. Looks like a very familiar RC low-pass filter now, huh?

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Method 1: Riso - Theory A quick analysis of the circuit shows that the transfer function from AOL to the actual amplifier output now is now comprised of a pole-zero response with the zero location at 1/(2*pi*Riso*Cload) and the pole location at 1/(2*pi*(Ro+Riso)*Cload)) Plotting this shows a reduction in the magnitude response with a -3dB point at the pole location and it flattening back off to 3dB above it’s final value of (Riso / (Riso + Ro) at the zero location. The phase response shows that the phase begins to decrease a decade before the pole frequency and continues to decrease until the zero begins to increase counteract the pole a decade before the zero location. The final result is a net 0degree phase shift through this network.

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**Method 1: Riso - Theory X =**

So to look at the effect on the final AOL graphically, we have the initial AOL of the OPA627 on the left multiplied by the response of the AOL output load. A multiplication is an addition in the log-domain which is how we obtain the final response shown in the bottom circuit. The pole begins reducing the AOL at the pole frequency and the phase is shifted to basically 0 degrees for a unity-gain system. =

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**Method 1: Riso - Design Ensure Good Phase Margin:**

1.) Find: fcl and f(AOL = 20dB) 2.) Set Riso to create AOL zero: Good: f(zero) = Fcl for PM ≈ 45 degrees. Better: f(zero) = F(AOL = 20dB) will yield slightly less than 90 degrees phase margin fcl = kHz f(AOL = 20dB) = 70.41kHz 1.5 decades ~ Fp * 35

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**Method 1: Riso - Design Ensure Good Phase Margin: Test fcl = 222.74kHz**

f(AOL = 20dB) = 70.41kHz → Riso = 2.26Ohms fcl = kHz → Riso = 0.715Ohms 1.5 decades ~ Fp * 35

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**Method 1: Riso - Design Prevent Phase Dip:**

Place the zero less than 1 decade from the pole, no more than 1.5 decades away Good: Decades: F(zero) ≤ 35*F(pole) → Riso ≥ Ro/34 → 70° Phase Shift Better: 1 Decade: F(zero) ≤ 10*F(pole) → Riso ≥ Ro/ → 55° Phase Shift Reminder that the pole does move with the zero. 1.5 decades ~ Fp * 35

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**Method 1: Riso - Design Prevent Phase Dip: Ratio of Riso to Ro**

If Riso ≥ 2*Ro → F(zero) = 1.5*F(pole) → ~10° Phase Shift **Almost completely cancels the pole. Reminder that the pole does move with the zero. 1.5 decades ~ Fp * 35

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**Method 1: Riso – Design Summary**

1.) Ensure stability by placing Fzero ≤ F(AOL=20dB) 2.) If Fzero is > 1.5 decades from F(pole) then increase Riso up to at least Ro/34 3.) If loads are very light consider increasing Riso > Ro for stability across all loads Reminder that the pole does move with the zero. 1.5 decades ~ Fp * 35

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**Method 1: Riso - Disadvantage**

Voltage drop across Riso may not be acceptable Showing the major negative factor about the isolation resistor which is the voltage drop when there is a load on the output.

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**Method 2: Riso + Dual Feedback**

The second method that we will look at uses an isolation resistor again to break capacitive load from the amplifier output. A high-frequency feedback is taken directly around the amplifier making a buffer driving Riso+Cload at high frequencies. The DC loop is closed on the other side of the isolation resistor so there isn’t a DC drop even with a load.

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**Method 2: Riso + Dual Feedback**

Theory: Features a low-frequency feedback to cancel the Riso drop and a high-frequency feedback to create the AOL pole and zero. The second method that we will look at uses an isolation resistor again to break capacitive load from the amplifier output. A high-frequency feedback is taken directly around the amplifier making a buffer driving Riso+Cload at high frequencies. The DC loop is closed on the other side of the isolation resistor so there isn’t a DC drop even with a load.

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**Method 2: Riso + Dual Feedback**

When to Use: Only practical solution for very large capacitive loads ≥ uF When DC accuracy must be preserved across different current loads The second method that we will look at uses an isolation resistor again to break capacitive load from the amplifier output. A high-frequency feedback is taken directly around the amplifier making a buffer driving Riso+Cload at high frequencies. The DC loop is closed on the other side of the isolation resistor so there isn’t a DC drop even with a load.

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**Method 2: Riso + Dual Feedback - Design**

Ensure Good Phase Margin: 1.) Find: fcl and f(AOL = 20dB) 2.) Set Riso to create AOL zero: Good: f(zero) = Fcl for PM ≈ 45 degrees. Better: f(zero) = F(AOL = 20dB) will yield slightly less than 90 degrees phase margin 3.) Set Rf so Rf >>Riso Rf ≥ (Riso * 100 4.) Set Cf ≥ (200*Riso*Cload)/Rf fcl = kHz f(AOL = 20dB) = 70.41kHz 1.5 decades ~ Fp * 35

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**Method 2: Riso + Dual Feedback - Summary**

Ensure Good Phase Margin (Same as “Riso” Method): 1.) Set Riso so f(zero) = F(AOL = 20dB) 2.) Set Rf: Rf ≥ (Riso * 100) 3.) Set Cf: Cf ≥ (200*Riso*Cload)/Rf 1.5 decades ~ Fp * 35

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**Capacitive Loads – Circuits with Gain**

So to look at the effect on the final AOL graphically, we have the initial AOL of the OPA627 on the left multiplied by the response of the AOL output load. A multiplication is an addition in the log-domain which is how we obtain the final response shown in the bottom circuit. The pole begins reducing the AOL at the pole frequency and the phase is shifted to basically 0 degrees for a unity-gain system.

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**Capacitive Loads – Circuits with Gain**

If the circuit has a noise gain greater than 0dB then there are a few other circuit options available for stabilizing the capacitive load.

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**Capacitive Loads – Circuits With Gain - Results**

Same Issues as Unity Gain Circuit Pole in AOL!! ROC = 40dB/decade!! Phase Margin = 10°!! Notice boost in phase margin from the gain. If the gain is greater than the magnitude of F(AOLpole) then the circuit will be at least marginally stable.

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**Stabilize Capacitive Loads – Circuits with Gain**

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Stability Options Circuits with gain can be stabilized by modifying the AOL load and by modifying 1/Beta

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Method 1 + Method 2 Methods 1 and 2 work on circuits with gain as well! Method 1: Riso Method 2: Riso+Dual Feedback

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Method 3: Cf The second method that we will look at uses an isolation resistor again to break capacitive load from the amplifier output. A high-frequency feedback is taken directly around the amplifier making a buffer driving Riso+Cload at high frequencies. The DC loop is closed on the other side of the isolation resistor so there isn’t a DC drop even with a load.

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Method 3: Cf - Results Theory: 1/Beta compensation. Cf feedback capacitor causes 1/Beta to decrease at -20dB/decade and if placed correctly will cause the ROC to be 20dB/decade.

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Method 3: Cf - Results When to use: Especially effective when NG is high, ≥ 30dB. Systems where a bandwidth limitation is not an issue - Limits closed-loop bandwidth at 1/(2*pi*Rf*Cf)

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**Method 3: Cf - Design Ensure Good Phase Margin:**

For 20dB/decade ROC, 1/Beta must intersect AOL while its slope is -20dB/decade. Therefore: f(1/B pole) < f(cl_unmodified) f(1/B zero) > f(AOL = 0dB) f(cl_unmodified) = kHz f(AOL = 0dB) = kHz

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**Method 3: Cf - Design Ensure Good Phase Margin:**

1.) Find f(AOL=0dB) 2.) Set f(1/B zero) by choosing Cf: Good: Set f(1/B zero) = f(AOL = 0dB) for PM ≈ 45 degrees. Better: Set f(1/B zero) so f(cl) = ½ Low-Frequency NG in dB f(AOL = 0dB) = kHz

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**Method 3: Cf – Design - Summary**

1.) Ensure stability by placing: a) f(1/B zero) ≥ f(AOL = 0dB b) f(1/B pole) ≤ f(cl_unmodified) 2.) Try to adjust the zero location so the 1/B curve crosses the AOL curve in the middle of the /B span allowing for shifts in AOL

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Method 4: Noise-Gain The second method that we will look at uses an isolation resistor again to break capacitive load from the amplifier output. A high-frequency feedback is taken directly around the amplifier making a buffer driving Riso+Cload at high frequencies. The DC loop is closed on the other side of the isolation resistor so there isn’t a DC drop even with a load.

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**Method 4: Noise Gain - Results**

Theory: 1/Beta compensation. Raise high-frequency 1/Beta so the ROC occurs before the AOL pole causes the AOL slope to change

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**Method 4: Noise Gain - Results**

When to use: Better for lighter capacitive loading When f(AOL pole) < (Closed loop gain + 20dB) Due to the increase in noise gain, this approach may not be practical when required noise gain is greater than the low-frequency signal gain by more than ~25-30dB.

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**Method 4: Noise Gain - Design**

Ensure Good Phase Margin: For 20dB/decade ROC, 1/Beta must intersect AOL above the AOL pole. Therefore: |High-Freq NG| > f(AOL pole) f(1/B zero) < f(AOL = High-Freq NG) f(AOL pole) = 52.11dB f(AOL pole) = 29.49kHz AC Noise Gain must be > fAOLpole Phase drops too low in loop if Fp and Fz are more than 1.5 decades apart.

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**Method 4: Noise Gain - Design**

Ensure Good Phase Margin: 1.) Find f(AOL pole) and f(AOL pole) 2.) Set High-Freq Noise-Gain by choosing Rn: Good: |HF NG| ≥ f(AOL pole) Better: |HF NG| ≥ f(AOL pole) + 10dB f(AOL pole) = 52.11dB f(AOL pole) = 29.49kHz AC Noise Gain must be > fAOLpole Phase drops too low in loop if Fp and Fz are more than 1.5 decades apart.

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**Method 4: Noise Gain - Design**

Ensure Good Phase Margin: 3.) Find f(cl_modified) = |HF NG|) 4.) Set f(1/B zero) by choosing Cn: Good: f(1/B zero) ≤ f(cl_modified) Better: f(1/B zero) ≤ f(cl_modified) / 3.5 (~ ½ decade) f(cl_modified) = 29.49kHz AC Noise Gain must be > fAOLpole Phase drops too low in loop if Fp and Fz are more than 1.5 decades apart.

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**Method 4: Noise Gain - Summary**

1.) Ensure stability by setting: a) |HF NG| ≥ f(AOL pole) + 10dB) b) f(1/B zero) ≤ f(cl_modified) / 3.5 AC Noise Gain must be > fAOLpole Phase drops too low in loop if Fp and Fz are more than 1.5 decades apart.

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Method 4: Noise Gain Quick reminder that inverting and non-inverting noise gain circuits are different!

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**Circuits with High Feedback Resistance**

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**Circuits with High Feedback Resistance**

The high feedback impedance of this amplifier circuit interacts with any stray capacitance and the input capacitance of the amplifier and causes instability.

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**Circuits with High Feedback Resistance**

Determine the Problem Zero in 1/Beta AOL unaffected Phase Margin 0!!

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**Circuits with High Feedback Resistance**

Looking at the open-loop circuit shows that the AOL is basically unaffected, but the beta circuit will change as the Cin capacitor shorts out the Rg resistor.

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**Circuits with High Feedback Resistance**

Pole in Beta is Zero in 1/Beta The result is a pole in the Beta response which will translate to a zero in the 1/Beta response. As mentioned previously, a zero in 1/Beta will cause stability issues. F(Pole) = 1/(2*pi*Cin*(Rf||Rg))

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**Stabilize Circuits With High Feedback Resistance**

So to look at the effect on the final AOL graphically, we have the initial AOL of the OPA627 on the left multiplied by the response of the AOL output load. A multiplication is an addition in the log-domain which is how we obtain the final response shown in the bottom circuit. The pole begins reducing the AOL at the pole frequency and the phase is shifted to basically 0 degrees for a unity-gain system.

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**Method 1: Cf Method 1 – 1/Beta Compensation, “Cf”**

Theory: Cf feedback places a pole in 1/Beta to cancel the zero from the input capacitance. When to use: Almost always a safe design practice. Limits gain at 1/(2*pi*Rf*Cf)

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**Method 1: Cf Method 1 – 1/Beta Compensation, “Cf”**

1/Beta Pole at 1/(2*pi*Rf*Cf)

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**Questions/Comments? Thank you!! Special Thanks to: Art Kay Bruce Trump**

Tim Green PA Apps Team

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