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1 IKI10230 Pengantar Organisasi Komputer Kuliah no. 4: CISC vs. RISC Instruction Sets 12 Maret 2003 Bobby Nazief Qonita Shahab

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Presentation on theme: "1 IKI10230 Pengantar Organisasi Komputer Kuliah no. 4: CISC vs. RISC Instruction Sets 12 Maret 2003 Bobby Nazief Qonita Shahab"— Presentation transcript:

1 1 IKI10230 Pengantar Organisasi Komputer Kuliah no. 4: CISC vs. RISC Instruction Sets 12 Maret 2003 Bobby Nazief Qonita Shahab bahan kuliah: Sumber: 1. Hamacher. Computer Organization, ed Materi kuliah CS61C/2000 & CS152/1997, UCB.

2 2 Review: Jenis-jenis Operasi Data Transfersmemory-to-memory move register-to-register move memory-to-register move Arithmetic & Logicinteger (binary + decimal) or FP Add, Subtract, Multiply, Divide not, and, or, set, clear shift left/right, rotate left/right Program Sequencing & Control unconditional, conditional Branch call, return trap, return Synchronizationtest & set (atomic r-m-w) Stringsearch, translate Graphics (MMX)parallel subword ops (4 16bit add) Input/Output Transfersregister-to-i/o device move

3 3 Review: Modus Pengalamatan (1/2) JenisSyntaxEffective Address 1.Immediate:#Value; Operand = Value Add #10,R1; R1  [R1] Register:Ri; EA = Ri Add R2,R1; R1  [R1] + [R2] 3.Absolute (Direct):LOC; EA = LOC Add 100,R1; R1  [R1] + [100] 4.Indirect-Register:(Ri); EA = [Ri] Add (R2),R1; R1  [R1] + [[R2]] Indirect-Memory:(LOC); EA = [LOC] Add (100),R1; R1  [R1] + [[100]]

4 4 Review: Modus Pengalamatan (2/2) 5.Index:X(R2); EA = [R2] + X Add 10(R2),R1; R1  [R1] + [[R2]+10] Base+Index:(R1,R2); EA = [R1] + [R2] Add (R1,R2),R3; R3  [R3] + [[R1]+[R2]] Base+Index+Offset:X(R1,R2); EA = [R1] + [R2] + X Add 10(R1,R2),R3 ; R3  [R3] + [[R1]+[R2]+10] 6.Relative:X(PC); EA = [PC] + X Beq 10 ; if (Z==1) then PC  [PC]+10 7.Autoincrement:(Ri)+; EA = [Ri], Increment Ri Add (R2)+,R1; R1  [R1] + [[R2]], ; R2  [R2] + d 8.Autodecrement:-(Ri); Decrement Ri, EA = [Ri] Add -(R2),R1; R2  [R2] – d, ; R1  [R1] + [[R2]]

5 5 Solusi PR #1 °2.8 A x X + C x D pada single-accumulator processor LoadA MultiplyB; Accumulator = A x B StoreX; X can be A, B, or others except C or D LoadC MultiplyD; Accumulator = C x D AddX; Accumulator = A x B + C x D

6 6 Solusi PR #1 °2.9 Jumlah nilai dari N siswa, J tes; J >> jumlah register Move#SUM,R0; R0 points to SUM MoveJ,R1; R1 = j MoveR1,R2 Add#1,R2 Multiply#4,R2; R2 = (j + 1)*4 Lj: Move#LIST,R3; R3 points to first student MoveJ,R4 SubR1,R4; R4: index to particular test of first student Multiply#4,R4 AddR4,R3; R3 points to particular test of first student MoveN,R4; R4 = n ClearR5; Reset the accumulator Ln: Add(R3),R5; Accumulate the sum particular test AddR2,R3; R3 points to particular test of next student DecrementR4 Branch>0Ln; Iterate for all students MoveR5,(R0); Store the sum of particular test Add#4,R0; R0 point to sum of the next test DecrementR1 Branch>0Lj; Iterate for all tests

7 7 Solusi PR #1 °2.10 (a) “Dot product” pada arsitektur Load/Store Move#AVEC,R1; R1 points to vector A. Move#BVEC,R2; R2 points to vector B. LoadN,R3; R3 serves as a counter. ClearR0; R0 accumulates the product. LOOP: Load(R1)+,R4 Load(R2)+,R5 MultiplyR5,R4; Compute the product of next ; components. AddR4,R0; Add to previous sum. DecrementR3; Decrement the counter. Branch>0LOOP; Loop again if not done. StoreR0,DOTPROD; Store the product in memory.

8 8 Solusi PR #1 °2.13 Effective Address R1 = 1200, R2 = 4600 Load20(R1),R5; EA = [R1] + 20 = = 1220 Move#3000,R5; EA = tidak ada (#3000: immd. value) StoreR5,30(R1,R2); EA = [R1] + [R2] + 30 = 5830 Add-(R2),R5; EA = [R2] – 1 = 4600 – 1 = 4599 Subtract(R1)+,R5; EA = [R1] = 1200

9 9 Solusi PR #1 °2.14 Linked list Move#1000,R0 ClearR1 ClearR2 ClearR3 LOOP: Add8(R0),R1 Add12(R0),R2 Add16(R0),R3 Move4(R0),R0 Compare#0,R0 BNELOOP MoveR1,SUM1 MoveR2,SUM2 MoveR3,Sum3

10 10 RISC vs. CISC

11 11 RISC vs. CISC °RISC = Reduced Instruction Set Computer Term coined at Berkeley, ideas pioneered by IBM, Berkeley, Stanford °RISC characteristics: Load-store architecture Fixed-length instructions (typically 32 bits) Three-address architecture Simple operations °RISC examples: MIPS, SPARC, IBM/Motorola PowerPC, Compaq Alpha, ARM, SH4, HP-PA,... °CISC = Complex Instruction Set Computer Term referred to non-RISC architectures °CISC characteristics: Register-memory architecture Variable-length instructions Complex operations °CISC examples: Intel 80x86, VAX, IBM 360, …

12 12 MIPS

13 13 MIPS I Registers °Programmable storage 2^32 x bytes of memory 31 x 32-bit GPRs (R0 = 0) 32 x 32-bit FP regs (paired DP) HI, LO, PC

14 14 MIPS Addressing Modes/Instruction Formats oprsrtrd immed register Register (direct) oprsrt register Base+index + Memory immedoprsrt Immediate immedoprsrt PC PC-relative + Memory All instructions 32 bits wide Destination first:OPcodeR dest,R src1,R src2

15 15 MIPS Data Transfer Instructions InstructionComment SW500(R4), R3Store word SH502(R2), R3Store half SB41(R3), R2Store byte LWR1, 30(R2)Load word LHR1, 40(R3)Load halfword LHUR1, 40(R3)Load halfword unsigned LBR1, 40(R3)Load byte LBUR1, 40(R3)Load byte unsigned LUIR1, 40Load Upper Immediate (16 bits shifted left by 16) 0000 … 0000 LUI R5 R5

16 16 MIPS Arithmetic Instructions InstructionExampleMeaningComments add add $1,$2,$3$1 = $2 + $33 operands subtractsub $1,$2,$3$1 = $2 – $33 operands add immediateaddi $1,$2,100$1 = $ constant add unsignedaddu $1,$2,$3$1 = $2 + $33 operands subtract unsignedsubu $1,$2,$3$1 = $2 – $33 operands add imm. unsign.addiu $1,$2,100$1 = $ constant multiply mult $2,$3Hi, Lo = $2 x $364-bit signed product multiply unsignedmultu$2,$3Hi, Lo = $2 x $364-bit unsigned product divide div $2,$3Lo = $2 ÷ $3, Hi = $2 mod $3 divide unsigned divu $2,$3Lo = $2 ÷ $3, Hi = $2 mod $3 Move from Himfhi $1$1 = HiUsed to get copy of Hi Move from Lomflo $1$1 = LoUsed to get copy of Lo

17 17 MIPS Logical Instructions InstructionExampleMeaningComment and and $1,$2,$3$1 = $2 & $33 reg. operands oror $1,$2,$3$1 = $2 | $33 reg. operands xorxor $1,$2,$3$1 = $2  $33 reg. operands nornor $1,$2,$3$1 = ~($2 |$3)3 reg. operands and immediateandi $1,$2,10$1 = $2 & 10Logical AND reg, constant shift left logicalsll $1,$2,10$1 = $2 << 10Shift left by constant shift right logicalsrl $1,$2,10$1 = $2 >> 10Shift right by constant shift right arithm.sra $1,$2,10$1 = $2 >> 10Shift right (sign extend) shift left logicalsllv $1,$2,$3$1 = $2 << $3 Shift left by variable shift right logicalsrlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable shift right arithm.srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable

18 18 MIPS Compare and Branch Instructions °Compare and Branch BEQ rs, rt, offset if R[rs] == R[rt] then PC-relative branch BNE rs, rt, offset <> °Compare to zero and Branch BLEZ rs, offset if R[rs] <= 0 then PC-relative branch BGTZ rs, offset > BLT < BGEZ >= BLTZAL rs, offset if R[rs] < 0 then branch and link (into R 31) BGEZAL >=

19 19 MIPS Compare and Set, Jump instructions InstructionExampleMeaning set on less thanslt $1,$2,$3if ($2 < $3) $1=1; else $1=0 Compare less than; 2’s comp. set less than immslti $1,$2,100if ($2 < 100) $1=1; else $1=0 Compare < constant; 2’s comp. set less than uns.sltu $1,$2,$3if ($2 < $3) $1=1; else $1=0 Compare less than; natural numbers set l. t. imm. uns.sltiu $1,$2,100if ($2 < 100) $1=1; else $1=0 Compare < constant; natural numbers jumpj 10000go to Jump to target address jump registerjr $31go to $31 For switch, procedure return jump and linkjal 10000$31 = PC + 4; go to For procedure call

20 20 MIPS I/O Instructions °MIPS tidak memiliki instruksi khusus untuk I/O °I/O diperlakukan sebagai “memori”  Status Register & Data Register “dianggap” sebagai memori

21 21 Contoh Program: Vector Dot Product LUIR1,high(AVEC); R1 points to vector A. ORIR1,R1,low(AVEC) LUIR2,high(BVEC) ; R2 points to vector B. ORIR2,R2,low(BVEC) LUIR6,high(N) LWR3,low(N)(R6); R3 serves as a counter. ANDR4,R4,R0; R4 accumulates the product. LOOP:LWR5,0(R1); Compute the product of LWR6,0(R2); next components. MULTR5,R5,R6 ADDR4,R4,R5; Add to previous sum. ADDIR3,R3,-1; Decrement the counter. BNER3,R0,LOOP; Loop again if not done. LUIR6,high(DOTPROD); Store the product in memory. SWlow(DOTPROD)(R6),R4

22 22 x86

23 23 Intel History: ISA evolved since 1978 °8086: 16-bit, all internal registers 16 bits wide; no general purpose registers; ‘78 °8087: + 60 Fl. Pt. instructions, (Prof. Kahan) adds 80-bit-wide stack, but no registers; ‘80 °80286: adds elaborate protection model; ‘82 °80386: 32-bit; converts 8 16-bit registers into 8 32-bit general purpose registers; new addressing modes; adds paging; ‘85 °80486, Pentium, Pentium II: + 4 instructions °MMX: + 57 instructions for multimedia; ‘97 °Pentium III: +70 instructions for multimedia; ‘99 °Pentium 4: +144 instructions for multimedia; '00

24 24 x86 Registers Program Counter (PC)

25 25 Organization of Segment Registers

26 26 Instruction Format °Ukuran instruksi [n] bervariasi: 1  n  16 byte 0, 1, 2, 3, 4 1, 2 0,1 0,1 0, 1, 2, 3, 4 0, 1, 2, 3, 4 Prefix: (Lock, Repeat), Overrides: Segment, Operand Size, Address Size ModR/M: Addressing Mode SIB: Scale, Index, Base Displacement: Displacement’s Value Immediate: Immediate’s Value °Konvensi:OPcode dst,src; dst  dst OP src MOV AL,BL; byte (8 bit) MOV AX,BX; word (16 bit) MOV EAX,EBX; double-word (32 bit) PrefixDisplacementImmediate SIB Opcode Mod R/M

27 27 Addressing Modes °Immediate °Register °Direct (Absolute) °Indirect (Register) °Index:

28 28 Addressing Modes: Contoh °Immediate: MOVEAX,25; EAX  25 MOVEAX,NUM; NUM: konstanta °Register: MOVEAX,EBX; EAX  [EBX] °Direct (Absolute): MOVEAX,LOC; EAX  [LOC] ; LOC: label alamat MOVEAX,[LOC] ; EAX  [LOC] °Register Indirect: MOVEBX,OFFSET LOC; EBX  #LOC MOVEAX,[EBX]; EAX  [[EBX]] °Index: Base+disp.:MOVEAX,[EBP+10]; EAX  [EBP+10] Index+disp.:MOVEAX,[ESI*4+10]; EAX  [ESI*4+10] Base+Index:MOVEAX,[EBP+ESI*4]; EAX  [EBP+ESI*4] Base+Index+disp.:MOVEAX,[EBP+ESI*4+10] ; EAX  [EBP+ESI*4+10]

29 29 Data Transfer Instructions °MOV Move °PUSH Push onto stack °PUSHA/PUSHAD Push GP registers onto stack °XCHG Exchange °CWD/CDQConvert word to doubleword/Convert doubleword to quadword °XLATTable lookup translation °CMOVEConditional move if equal °CMOVNEConditional move if not equal °CMPXCHG Compare and exchange

30 30 Arithmetic Instructions °Binary Arithmetic: ADD, ADC, SUB, SBB IMUL, MUL, IDIV, DIV INC, DEC, NEG, CMP °Decimal Arithmetic: DAA Decimal adjust after addition DAS Decimal adjust after subtraction AAA ASCII adjust after addition AAS ASCII adjust after subtraction

31 31 Logical Instructions °ANDAnd °OROr °XORExclusive or °NOTNot °… °SAR/LShift arithmetic right/left °SHR/LShift logical right/left °SHRDShift right double °SHLDShift left double °ROR/LRotate right/left °RCR/LRotate through carry right/left

32 32 Branch Instructions °JMP Jump °JE/JZ Jump if equal/Jump if zero °JNE/JNZ Jump if not equal/Jump if not zero °JC Jump if carry °JNC Jump if not carry °JCXZ/JECXZ Jump register CX zero/Jump register ECX zero °LOOP Loop with ECX counter °INT Software interrupt °IRET Return from interrupt

33 33 I/O Instructions °INRead from a port °OUTWrite to a port

34 34 String °MOVS/MOVSB Move string/Move byte string °MOVS/MOVSW Move string/Move word string °MOVS/MOVSD Move string/Move doubleword string °INS/INSB Input string from port/Input byte string from port °OUTS/OUTSB Output string to port/Output byte string to port °CMPS/CMPSB Compare string/Compare byte string °SCAS/SCASB Scan string/Scan byte string °REP Repeat while ECX not zero °REPE/REPZ Repeat while equal/Repeat while zero °REPNE/REPNZ Repeat while not equal/Repeat while not zero

35 35 HLL Support & Extended Instruction Sets °HLL Support: BOUND Detect value out of range ENTER High-level procedure entry; creates a stack frame LEAVE High-level procedure exit; reverses the action of previous ENTER °Extended: MMX Instructions -Operate on Packed (64 bits) Data simultaneously  use 8 MMX Register Set Floating-point Instructions System Instruction Streaming SIMD Extensions -Operate on Packed (128 bits) Floating-point Data simultenously  uses 8 XMMX Register Set

36 36 Contoh Program: Vector Dot Product LEAEBP,AVEC; EBP points to vector A. LEAEBX,BVEC ; EBX points to vector B. MOVECX,N; ECX serves as a counter. MOVEAX,0; EAX accumulates the product. MOVEDI,0; EDI is an index register. LOOPSTART:MOVEDX,[EBP+EDI*4] ; Compute the product of IMULEDX,[EBX+EDI*4] ; next components. INCEDI; Increment index. ADDEAX,EDX; Add to previous sum. LOOPLOOPSTART; Loop again if not done. MOVDOTPROD,EAX ; Store the product in memory.

37 37 MIPS (RISC) vs. Intel 80x86 (CISC)

38 38 MIPS vs. Intel 80x86 °MIPS: “Three-address architecture” Arithmetic-logic specify all 3 operands add $s0,$s1,$s2 # s0=s1+s2 Benefit: fewer instructions  performance °x86: “Two-address architecture” Only 2 operands, so the destination is also one of the sources add $s1,$s0 # s0=s0+s1 Often true in C statements: c += b; Benefit: smaller instructions  smaller code

39 39 MIPS vs. Intel 80x86 °MIPS: “load-store architecture” Only Load/Store access memory; rest operations register-register; e.g., lw $t0, 12($gp) add $s0,$s0,$t0 # s0=s0+Mem[12+gp] Benefit: simpler hardware  easier to pipeline, higher performance °x86: “register-memory architecture” All operations can have an operand in memory; other operand is a register; e.g., add 12(%gp),%s0 # s0=s0+Mem[12+gp] Benefit: fewer instructions  smaller code

40 40 MIPS vs. Intel 80x86 °MIPS: “fixed-length instructions” All instructions same size, e.g., 4 bytes simple hardware  performance branches can be multiples of 4 bytes °x86: “variable-length instructions” Instructions are multiple of bytes: 1 to 16;  small code size (30% smaller?) More Recent Performance Benefit: better instruction cache hit rates Instructions can include 8- or 32-bit immediates

41 41 MIPS vs. x86: Code Length LUIR1,high(AVEC) ORIR1,R1,low(AVEC) LUIR2,high(BVEC) ORIR2,R2,low(BVEC) LUIR6,high(N) LWR3,low(N)(R6) ANDR4,R4,R0 LOOP:LWR5,0(R1) LWR6,0(R2) MULTR5,R5,R6 ADDR4,R4,R5 ADDIR3,R3,-1 BNER3,R0,LOOP LUIR6,high(DOTPROD) SWlow(DOTPROD)(R6),R4 LEAEBP,AVEC LEAEBX,BVEC MOVECX,N MOVEAX,0 MOVEDI,0 LOOPSTART:MOVEDX,[EBP+EDI*4] IMULEDX,[EBX+EDI*4] INCEDI ADDEAX,EDX LOOPLOOPSTART MOVDOTPROD,EAX


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