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By Marek Lis Sr Application Engineer Texas Instruments -Tucson

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1 By Marek Lis Sr Application Engineer Texas Instruments -Tucson
Understanding Operational Amplifier Limitations and Long-Term Stability By Marek Lis Sr Application Engineer Texas Instruments -Tucson

2 Summary of Topics Review of Op-Amp Input Topologies
Common Mode limits Causes of Op-Amp Output Phase Inversion Bipolar vs. JFET input effects caused by exceeding the Vcm Review of Op-Amp Output Topologies Output Swing limits Long-Term Stability Spec for specs centered around a fixed value for parameters specified as an absolute value

3 Input Stage Considerations

4 REAL WORLD Vcm Input Range
Common mode voltage on op amps is normally defined as the average voltage on the amplifier input pins with respect to the supplies. Remember that the voltage on each input is approximately equal (i.e. virtual short). The common mode range is the range of usable common mode voltages for a given amplifier. When an amplifier is used outside of the common mode voltage range it will not respond linearly and will not meet data sheet specifications. Common mode range is also given with respect to the supplies. As shown in the figure some amplifiers have common mode range slightly beyond the negative supply or positive supply. Some amplifiers common mode range is a few volts from either supply. The best case scenario is shown in the lower right corner. This amplifier has common mode voltage range slightly beyond each power supply rail. This is called a rail to rail amplifier. This section of the presentation will cover each of these possibilities. This section will also show how the internal circuitry operation limits the common mode range. Strictly speaking it is not necessary to understand the transistor implementation of op-amps to use them in system designs. However, having some understanding of the internal implementation gives useful insight into system level performance.

Each amplifier has 36V supplies! The common mode in each case is the supply midpoint. All amps can act as “single supply” This slide emphasizes that fact that the offset of an amplifier will not change if the total supply voltage is constant and the common mode voltage is kept at the same point relative to the power supply. In this example each amplifier has a total supply voltage of 36V. The common mode is set at the mid point (1/2 supply) for each example. Note that the offset is not changed. The point is to dispel the notion that you need a “single supply amplifier” to shift the supplies. All op-amps can operate with shifted supplies. The key is to be careful to observe common mode restrictions. Amplifiers that are called “single supply amplifiers” are normally optimized to allow common mode voltage to the negative supply. Note: A single-supply optimized op amp is not the same as a single supply op amp.

6 MOSFET Simple Input (Vcm to negative rail)
An example of a typical MOSFET input type. These inputs can swing slightly below GND and a volt to several volts below the positive supply. For example, the single supply configuration shown on the left allows inputs from -0.2V to 4V. Any input below -0.2V or above 4V will not produce a linear output.

7 Simplified schematic of OPA336 input stage (Swing to Positive Rail)
This example shows MOSFET common mode limitations for the positive rail. The example makes some simplifications, but is representative of the types of issues that limit common mode range. In this example the maximum voltage on an input can be seen by doing a Kirchhoff's voltage walk from the negative supply (Vin < Vsat + Vgs). In this example Q4 is cuttoff. Trying to drive the input to a larger voltage will not allow for linear output changes. In this example: Vin < Vsat + Vgs Vin < 0.9V + 0.1V Vin < 1.0V for linear operation

8 Simplified schematic of OPA336 input stage (Swing to Negative Rail)
This example shows MOSFET common mode limitations for the negative rail. The example makes some simplifications, but is representative of the types of issues that limit common mode range. In this example the minimum voltage on an input can be seen by doing a Kirchhoff's voltage walk from the negative supply (Vin > Vce + Vsat – Vgs). In this example Q4 is saturated. Trying to drive the input to a lower voltage will not allow for linear output changes. In this example: Vin > Vce + Vsat – Vgs Vin < 0.6V + 0.1V -0.9V Vin < -0.2V for linear operation

9 Typical Bipolar or JFET Input (not rail-to-rail)
This slide illustrates an amplifier that has common mode limitations to both supplies. In this example, the input voltage is limited to 3V below the positive rail and 3V below the negative rail. The example circuit at the bottom of the page shows the input common mode range with asymmetrical supplies. In this example the amplifier would not respond linearly if the input signal is below -2V or above 9V.

10 Simplified schematic of OPA827 input stage Swing to Negative Rail
This example shows a typical JFET / Bipolar input stage. In this example we will only look at swing to the negative rail. In this example the minimum voltage on an input can be seen by doing a Kirchhoff's voltage walk from the negative supply (Vin > VR2 + VBE + VBE + VSAT - VGS). In this example Q4 is saturated. Trying to drive the input to a lower voltage will not allow for linear output changes. In this example: Vin > VR2 + VBE + VBE + VSAT - VGS Vin < 0.1V + 0.7V + 0.7V+0.1V – 0.9V ********* ???????? What are the correct numbers ??????? Vin < 3V for linear operation The example shown is simplified. Analyzing the swing to the positives rail would use similar techniques would require the full schematic.

11 MOSFET Complementary N-P-FET (rail-to-rail)
This slide shows a Rail-to-Rail input that uses a complementary PFET and NFET input stage. On a rail-to-rail amplifier the input common mode range extends below the negative rail and above the positive rail. The circuit example at the left shows a single supply arrangement. In this example, the input common mode signal can range from -0.3V to 5.3V for linear operation. If the signal is above 5.3V or below -.3V the amplifier will not respond linearly.

12 Simplified schematic of OPA703 input stage
This slide illustrates how two separate p-channel and n-channel input differential pairs can be used to make a rail-to-rail amplifier. The idea is that the p-channel input pair can have common mode range slightly below the negative supply and the n-channel input pair can have common mode range slightly above the positive rail. A p-channel device (T8) is used in this case control which of the two input pairs is actively biased. For the lower common mode range the p-channel pair is biased. When the common mode voltage is about 2V from the positive rail T8 diverts current from the p-channel input pair to the n-channel pair. For common mode voltages less then 2V from the positive rail the n-channel pair is biased. Note that there is a region where both pairs share the bias (the transition zone).

13 OPA703 Complementary CMOS (rail-to-rail)
The two different input pairs will both have independent and uncorrelated input offset voltages. In most cases this means that the input offset will be different for the two different input pairs. Thus when we transition from one pair to the other, the offset will abruptly change values. The figure above show the abrupt transition in input offset voltage. The red region illustrates that the p-channel input pair is active for common mode voltage from -0.3V to 3V. The p-channel pair has an offset of about 100uV. The green region illustrates that the n-channel input pair is active for common mode voltage from 3V to 5V. The n-channel pair has an offset of about -200uV. When the common mode transitions past 3V the offset transitions from 100uV to -200uV. The abrupt transition in offset products “crossover distortion” in the output signal. Also you will notice that the common mode rejection is poor if the entire common mode range is considered. In some amplifier specifications you will see two separate specifications for common mode rejection (CMR) in the two different regions. In this case the CMR of each region can be very good but the overall CMR will be poor if you include the crossover distortion.

14 MOSFET Charge Pump (rail-to-rail)
Another method for creating a rail-to-rail amplifier is to use an internal charge pump. The advantage of using the charge pump is that the amplifier will no longer have crossover distortion. Notice the high common mode rejection (CMRR = 120dB for OPA365) of this device compared to the complementary input design (CMRR=90 for OPA703). The next slide will show how the charge pump design allows for rail-to-rail common mode range.

15 Remember from Earlier in the presentation…
The limit is based on the positive supply minus saturation voltage and Vgs. The slide above is a reminder that the simple p-channel input stage positive supply limitation is the saturation voltage of the current source plus the gate to source on voltage for the p-channel FET. Boosting the supply voltage internally can overcome this limitation because the input swing is now related to the internal supply.

16 MOSFET Charge Pump OPA363 (rail-to-rail)
Supplies a small current to input GBW = 50MHz, Charge Pump Freq=10MHz This shows a simplified representation of the charge pump used on OPA363 to make the input rail to rail. Note that this circuit will not have the cross over issue associated with the complementary p-n input stage. The charge pump does not need to supply much current to the input pair. In this case the charge pump boosts the supply voltage by 1.8V. This is enough to overcome the Vsat + Vgs positive rail limitation on the p-channel input pair. On concern that often accompanies charge pump circuits is that they use a switched capacitor implementation to boost the dc voltage. The switching generates noise; however, in this case the amount of noise is minimized by the very low ripple design. Nevertheless, it is possible to see this noise in some cases. In this example the charge pump switches at 10MHz and the bandwidth of the amplifier is 50MHz. So in low gain the bandwidth will pass the charge pump signal. Generally the charge pump signal is small relative to the broadband noise of the amplifier. Also note that the charge pump signal can leave the amplifier and go onto the external power supply. In this case it can mix with other power supply noise and create harmonics of the charge pump signal. For this reason it is best to be very careful to do proper decoupling on the power supply. In some cases using a ferrite between the amplifier and other sensitive circuits may also help.

17 MOSFET Zero Drift (rail-to-rail)
The Zero-Drift amplifier uses a digital calibration method to greatly reduce input offset voltage and offset drift. We will go into some details of the zero drift amplifier later. This slide shows a rail-to-rail common mode input zero drift amplifier. All zero drift amplifiers do not necessarily rail-to-rail inputs. The reason for mentioning zero drift at this time is because the zero drift calibration greatly reduces the crossover distortion that was mentioned when we discussed complementary p-n inputs. Notice in this example that the amplifier has very good common mode rejection (130dB) over the entire common mode range.

18 MOSFET Zero Drift (rail-to-rail)
No Offset Correction This slide shows how zero drift amplifiers can minimize the crossover distortion effect. First it should be noted that zero drift amplifiers with rail-to-rail inputs use the same complementary n-channel and p-channel input configuration, so the zero drift amplifiers will exhibit crossover distortion. However, the offset is corrected by digital calibration, so the magnitude of the transition is greatly diminished. In the previous slide we saw that the OPA333 had a CMRR of 130dB (zero drift). A similar input structure without zero drift OPA703 had a CMRR of 90dB (not zero drift). With Offset Correction

19 Zero Drift Chopper Topology

20 Zero Drift Auto-Zero Topology

21 Input Bias Current in Chopper Op Amps

22 Op Amp Output Phase Inversion

23 Typical Case of Op Amp Phase Inversion due to exceeding Vcm
The slide above shows the input output relationship of an op-amp with phase inversion. The input signal is shown in blue the output signal is shown in red. The input signal is moved outside of the common mode range of the amplifier. An amplifier without phase inversion will not respond linearly when the input goes outside of the common mode range. So you would expect to see the output flatten out or clip when the input common mode range is exceeded. However, in the case of phase inversion the output will actually flip polarity to the opposite rail. This can be very problematic in some applications (e.g. control systems). Most modern amplifiers have anti-phase reversal circuitry in the design. Some older designs may exhibit this phenomena. In the next few slides we will discuss what internal circuitry will cause this to happen and how modern circuitry prevents it.

24 Phase inversion on a single transistor

25 PNP Bipolar Input Op Amp Low Common-Mode Limitation Normal Operation – No Phase Inversion
The figure above shows normal operation for this circuit. For Normal operation, the input signal needs to be greater then 0.9V. The common mode voltage limit can be seen by doing a kirchhoff's voltage walk starting at the input looking at Vbe and the saturation voltage of T9 then considering the Vbe for T10 and T11. Under normal conditions decreasing Vin+ will cause the current in T9 to increase and the collector voltage increase. This behavior will continue until Vin is dropped below the common mode limit. The next slide will show how phase inversion happens.

26 PNP Bipolar Input Op Amp Low Common-Mode Limitation Phase Inversion Issue!
When the input falls below the 1.2V common mode limit, the collector voltage can no longer continue to drop and maintain normal transistor operation. Normally the collector to base junction on a bipolar transistor is reverse bias and the bipolar transistor will invert the signal (collector relative to base). When the input signal drops below the common mode limit, the collector to base junction becomes forward biased and the collector signal starts to follow the input signal (no inversion collector to base). Thus the overall phase of the amplifier has changed because T9 is no longer inverting as it should.

27 An Example of IC Circuit used to Prevent a Phase Inversion

28 Summary of Output Phase Inversion
What causes a phase reversal? Exceeding the input common-mode voltage range may cause a phase reversal. How can it be prevented? Staying with op amp specified Vcm linear region Using op amp with a built-in anti-phase reversal circuitry Utilizing external circuitry to prevent a phase inversion Is it process dependent?  Some built-in anti-phase reversal circuitry might be process dependent depending on topology used Most modern op amps use a robust topologies assuring no phase reversal How can a customer be confidant of no phase reversal? (if it is not explicitly stated in the data sheet) Apply a slow triangular waveform in a buffer configuration 1V beyond rails to test for phase inversion - you must limit the input current to less than 10mA to prevent damaging IC

29 Op amp Input Protection Diodes

30 Op Amp Input Common-Mode Below Negative Rail

31 Op Amp Input Common-Mode Above Positive Rail

32 JFET Input Op Amp High Common-Mode Limitation to positive rail looks like “dc rail to rail” to negative rail shows phase inversion. Vsat=0.3V JFET saturation is soft. So sort of works and DC might not show a huge problem. Worse noise, BW, SR, THD, but DC may work.

33 Output Stage Considerations

34 REAL WORLD Outputs

35 Classic Output Stage Common-emitter output Current source driver
Headroom set by VBE+VCESAT Unity Gain VSAT VBE

36 OPA827 – Classic Output Short Circuit Limit OPA827 OPA827
Output Saturated

37 OPA827 – Classic Output The Table Output Swing is defined at:
Vout swing = 18V – 3V = ±15V Iout = 15V/1k = 15mA For Aol > 120dB As you approach the limit or increase ILOAD, Aol will decrease.

38 R-to-R Output Stage Common Collector or Common Drain
Vsat = 50mV to ≈ 1mV Vsat = 0.2V Common Collector or Common Drain Headroom set by VDSsat or VCEsat On bipolar sat is approximately 0.2V After sat Beta drops dramatically On FET sat is limited by output transistor scaling Can achieve very low sat values (e.g. mV) Size vs swing trade off on cmos.

39 R-to-R Output Stage Value of RLOAD affects AOL and Output Swing
the gain in the last stage is set by rout / gm rout decreases with loading

40 Why can’t we get Rail-to-Rail on CMOS? MOSFET Characteristic Curves
Some minimum drain to source voltage is required. Increasing current requires more Vgs.

41 Typical Rail-to-Rail Input/Output Topology

42 OPA211 – rail-to-rail Out (Bipolar)
Loading limits output swing and reduces Aol.

43 Achieving Output Swing to the Negative Rail

44 SS Pull Down Cheat Sheet
Part # Resistor Value for -5V Supply OPA335 40 kΩ OPA340 7.5 kΩ OPA343 OPA348 250 kΩ OPA350 2 kΩ OPA353 OPA333 20 kΩ Selected to sink quiescent current in output stage. Approximately ½ Iq.

45 Common Questions: Op Amp Output Range Consideration

46 Long-Term Stability

47 Gaussian (or Normal) Distribution
Statistical process control techniques are based upon the assumption that the distribution is normal. We want good yield. If we are going to have a high grade… Production must have tested millions of parts to get a curve this symmetrical. (actually it’s a fake distribution) Median here is to get the chart to look nice. St Dev=12.5; (95.4% within 2 stdev) It would be nice to have the Standard deviation lines come in later, but they are part of the picture. 68% within ±1 standard deviation 99.7% within ±3 standard deviations

48 Understanding Statistical Distributions (specs centered around a mean value)
Typical value is 1 sigma for ones centered around 0. Max is set here for 4 sigma but sometimes set for 3 sigma. Drift here is tested for 3 sigma but Vos is only tested for 4 sigma to maximize yield. Done to provide a specific spec with higher accuracy at the expense of yield.

49 Long-Term (10 year) Shift for Gaussian Distributions (Centered around a Mean Value)
Initial PDS Distribution (blue) vs Long-Term Parametric Shift (green) For 10 year life of a product.

50 Life-Time Vos and Vos Temp Drift Shift
Max LT Vos = 240uV Max LT Vos Drift = 2.0uV/C Life-Time Max Shift (ten-year) = Max Initial Value Long-Term Max Spec = 2 * Initial Spec

51 Life-Time Output Voltage Initial Accuracy Shift (specs centered around a fixed value)
Max LT Vref = +/-0.1%

52 Long-Term Vref Shift The initial shift (first few months) makes up the majority of change. Self curing of molding compound.

53 Single Ended Limit A typical MIN and MAX range is at least +/-3σ:
Mean = Typical MAX = Mean + 3σ (or greater) MIN = Mean - 3σ (or greater)

54 Long-Term Shift for Single-ended Specs
+/- 1dB = +/-10% +10% -10% 54

55 Reading Between the Lines (estimating max spec based on a typical value)
Numb Standard Deviations % chance of Pass Percent Chance of Fail 1 2 3 4 5 E-05 6 E-07 3 sigma 0.27% failures

56 Life-Time Shift Rule Summary
You may estimate the maximum expected parametric shift over any given period of time by using: 100% of the max (min) PDS guaranteed value in the case of specs centered around a mean value (Vos, Vref, Vos Drift, etc). 10% of the max (min) guaranteed value for parameters specified as a fixed positive value (IQ, AOL, PSRR, CMRR, etc). and pro-rate them based on the expected ten-year life of the product. You need to keep in mind that the long-term shift is not exactly a linear function of time - it is steeper (shifts faster) in the first year and slows down in the later years. It also usually excludes the first 30 days due to continuing self-curing of the molding compound used for packaging of IC. 

57 Thank you for your interest
Acknowledgments Contributed to this presentation: Art Kay & Todd Toporski

58 Appendix

59 HTOL (High Temperature Operating Life)
HTOL is used to measure the constant failure rate region in the bottom of the bathtub curve as well as assess the wear-out phase of the curve for some use conditions. Smaller sample sizes than EFR but are run for a much longer duration Jedec and QSS default are Ta=125C for 1000 hours Q100 is 1000 hours at max temperature for the device’s grade Most modern IC’s undergo HTOL at Ta=150C for 300 hours But how much is this simulating in the field? 59

60 The Arrhenius Equation
Process Rate = Ae-(Ea/kT) A = A constant Ea = Thermal activation energy in electron volts (eV) k = Boltzman’s constant, 8.62 x eV/K T = Absolute temperature in degrees Kelvin (degrees C ) 60

61 AF(T1 to T2) = e(Ea/k)(1/T2 - 1/T1)
Acceleration Factors Acceleration Factors are the ratio of the Process Rate at two temperatures. AF(T1 to T2) = e(Ea/k)(1/T /T1) A = A constant (has canceled out of the formula) Ea = Thermal activation energy in electron volts (eV) k = Boltzman’s constant, 8.62 x eV/K T = Absolute temperature in degrees Kelvin (degrees C ) 61

62 Acceleration Factors (Example)
Calculate the thermal acceleration factor (AF) between the stress test temperature and the product use temperature: T (life-test stress) =150C->423K T (application) =65C->338K Ea=0.7eV AF(150 to 65) = e(0.7eV/k)(1/ /398) = 125 This means every hour of stress at 150C is equivalent to 125 hours of use in the application at 65C. Thus, for example, 300 hour life-test at 150C would cause similar shift as 37,500 hours (125*300hrs), or about 4 years, in the field at 65C. 62

63 Comments, Questions, Technical Discussions Welcome:
Marek Lis (520)

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