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APPLIED SIGNAL PROCESSING AND IMPLEMENTATION (ASPI) Introduction for 7th semester Fall 2005 Embedded Systems group: pk, yml, abo, ssc, jmk, dlc, rab, oo.

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Presentation on theme: "APPLIED SIGNAL PROCESSING AND IMPLEMENTATION (ASPI) Introduction for 7th semester Fall 2005 Embedded Systems group: pk, yml, abo, ssc, jmk, dlc, rab, oo."— Presentation transcript:

1 APPLIED SIGNAL PROCESSING AND IMPLEMENTATION (ASPI) Introduction for 7th semester Fall 2005 Embedded Systems group: pk, yml, abo, ssc, jmk, dlc, rab, oo Dicom group: kjh, pr, uh,....

2 2 ASPI Introduction Outline 1.Rationale for ASPI 2.Basic ASPI Model (A 3 ) 3.Trends: S8 -> S9 -> S10 4.Course structure 5.Project examples: S8 – S9/S10 6.Lab facilities 7.Demonstrations 8.Conclusion

3 3 ASPI Introduction Rationale for ASPI/1 Embedded System: a collection of heterogeneous parts subject to stringent design constraint such as...

4 4 ASPI Introduction Rationale for ASPI/2 Embedded Systems Nokia 7710 From To

5 5 ASPI Introduction Rationale for ASPI/3 Shannon Beats Moore’s Law and Energy Plays a Major Role Processor Performance (~Moore’s Law) Battery Capacity Source: Jan Rabaey, Summer Course, 2000 Algorithmic Complexity (Shannon’s Law) 1G 2G 3G

6 6 ASPI Introduction Basic ASPI Model (A 3 ) Applications Algorithms Architectures For each application => many candidate algorithms For each algorithm => many implementation architectures => Large no. of solutions => Large Design Space => ASPI challenge Equalizer FIR/IIR DSP/FPGA

7 7 ASPI Introduction FPGA FPGA components: 1.Dedicated I/O blocks 2.Programmable LogicArrayBlocks (LAB) - combinatorial / seqential circuits - routing resources 3.Dedicated blocks - RAM blocks - multipliers - processors (ARM/PowerPC) 4.Development tools

8 8 ASPI Introduction FPGA

9 9 ASPI Introduction ASPI Design Principle SerialParallel Transform a serial specification into a combination of: Serial, parallel and pipelined units That satifies the design constraints: Area, Time => Power Pipelined

10 10 ASPI Introduction Trends: S8 -> S9 -> S10 Application: Non-Linear Signal Processing/Mobile Communication 1.Algorithm selection 2.Simulation 3.Architecture selection and mapping Example later Applications Algorithms Architectures 2 3 1

11 11 ASPI Introduction Compiler optimiser C code modifications Compiler optimization

12 12 ASPI Introduction Trends: S8 -> S9 -> S10 Application: Non-Linear Signal Processing/Mobile Communication Algorithm selection Simulation Architecture selection and modelling Design Space Exploration HW/SW Co-Design Applications Algorithms Architectures

13 13 ASPI Introduction Design Space Exploration Constraints: Area, Time => Power = Area*f clock Area Time Tmax Amax Possible solutions (A*T ~ K)

14 14 ASPI Introduction HW/SW Co-Design

15 15 ASPI Introduction Trends: S8 -> S9 -> S10 Applications Algorithms Architectures Implementing a complete design trajectory With solutions where properties satisfies constraints Constraints Properties

16 16 ASPI Introduction ASPI Course Structure Design Methodology 8.sem9.Sem Algorithm analysis HW compilers HW Platform analysisSW Platform analysis SW compilers Design Space Expoloration

17 17 ASPI Introduction 8th Semester Courses F8-1 FP8-12 FP8-9 FP8-13 Engineering Responsibilities Higher Order Statistical Analysis Joint Time Frequency Analysis DSP Algorithms and Architectures 1 ECTS SE FP8-16 FP8-19 FP8-18 Adaptive Systems Inverse Filtering and Deconvolution Multidimensional Signal Processing 2 ECTS 1 ECTS PE ASPI8-4 FP8-17 DSP Design Methodology Software Programmable Platform Analysis 0.6 ECTS 1.4 ECTS PE Project20 ECTS

18 18 ASPI Introduction 9th Semester Courses FP9-2Discrete-Time Kalman Filtering2 ECTSSE ASPI9-2A ASPI9-2B ASPI9-3 ASPI9-4 Mob9-2 HW/SW CoDesign HW Platform Analysis, Comp. & Optim. Non-linear Signal Processing Neural Networks Radio Communication III 2 ECTS 1 ECTS 1.4 ECTS PE EL Project22 ECTS EL : ELective Course

19 19 ASPI Introduction Technology Simulation tools / Language: Matlab/M Ptolemy/(M)any Design Trotter/C Processors / Language: ARM/ C ++, ASM TI /C++, ASM Blackfin/ C ++, ASM Microblaze/ C++, ASM NIOS/ C++, ASM Programmable Logic: Xilinx FPGA/ Handel-C Altera FPGA/ Handel-C

20 20 ASPI Introduction Technology Lab facilities Celoxica RC203 board Xilinx Virtex FPGA

21 21 ASPI Introduction Technology Lab facilities Altera Stratix board Altera Stratix FPGA

22 22 ASPI Introduction Technology Lab facilities Analog Devices Blackfin boardAnalog Devices Blackfin DSP

23 23 ASPI Introduction Project Examples: S8/S9/S10 1.S8 Noise Suppression in Speech 2.S9 FPGA implementation of a JPEG 2000 encoder/decoder 3.Reed Solomon Decoder for DVB-H Most projects involves external contacts in other research groups or companies

24 Noise Suppression in Speech ASPI 8, Gruppe 840 Søren Birk Sørensen Andreas Popp Michael Smed Kristensen

25 25 ASPI Introduction Agenda Applikation Systemoversigt Algoritme Princip i algoritme Resultater Arkitektur Implementation

26 26 ASPI Introduction Systemoversigt Krav Forbedring af taleforståelighed Forbedring af signal-støj-forhold (SNR) Acceptabel forsinkelse i systemet (latenstid)

27 27 ASPI Introduction Princip

28 28 ASPI Introduction Resultater SNR ikke væsentligt forbedret Taleforståelse: Fra ”Very poor” til ”Good” Latenstid: 35 ms

29 29 ASPI Introduction Implementation Dele af algoritmen blev implementeret på et TI TMS320C6713 udviklingsboard Floating point Varierende pipeline dybde 8 instruktioner i parallel Analysere resultat af compilering Efterfølgende optimering

30 30 ASPI Introduction Foretagede optimeringer Eksekveringstid Anden algoritme til autokorrelationsberegning Loop unrolling giver mere parallelitet Informere kompiler om dataafhængighed Udnyttelse af pipeline Anden divisionsberegning Kortere eksekveringstid

31 31 ASPI Introduction Resultat af optimering Autokorrelationsberegning cycles  2624 cycles 153% mere end estimeret minimum antal cycles Levinson funktion 3842 cycles  1122 cycles 26% mere end estimeret minimum antal cycles

32 9th semester project example ”FPGA implementation of a JPEG 2000 encoder/decoder”

33 Motivation JPEG2000 is up to six times more complex to implement than JPEG 2 complex DSP algorithms at the heart of JPEG2000 Discrete Wavelet Transform (DWT) Embedded Block Coding with Optimized Truncation (EBCOT) FPGAs provide the ability to accelerate arithmetic operations via parallel processing FPGA implementation of a JPEG2000 encoder/decoder JPEG2K Block diagram (encoder)

34 Project flow Analysis of reference C-code processing analysis (search for potential parallelism) memory analysis (memory requirements) Sketch an architecture based on the analysis (architectural exploration) FPGA implementation Handel-C language to describe the architecture Handel-C to FPGA (Celoxica Design-suite) Analysis -> architectural refinement FPGA implementation of a JPEG 2000 encoder/decoder

35 35 ASPI Introduction Application: from DVB-T to DVB-H FEC: RS(n,k,t) => RS(255, 191, 64) Constraints: Frame size: upto 2 MB Data rate: 2 MB/S Time constraint: ASAP S10 Project: Reed-Solomon Decoder Data Parity Data Nokia 7710

36 36 ASPI Introduction S10 Project: Reed-Solomon Decoder Complexity: Execution on ARM: 22 min/2MB frame

37 37 ASPI Introduction S10 Project: Reed-Solomon Decoder Algorithm: Galois field arithmetic GF(2 8 ) Data: 8 bit bytes operators: binary +, *, not Properties: no carry, overflow or rounding error => bitwise operations In parallel Short critical path (delay) => high clock rate Identification of parallelism coarse function level fine operations level

38 38 ASPI Introduction S10 Project: Reed-Solomon Decoder Results: Execution on ARM: 22 min/2MB frame Parallelism: the error locator and the evaluator polynomial can be computed concurrently Reusable DataPath: Syndrome computation, Chien Search, polynomial evaluation and error correction can be performed on the same parallel DataPath

39 39 ASPI Introduction S10 Project: Reed-Solomon Decoder Results: DataPath: 65 8 bit blocks Design Space Exploration:

40 40 ASPI Introduction S10 Project: Reed-Solomon Decoder (DSE)

41 41 ASPI Introduction Conclusion ASPI salient features: based on Models and Methods application independent but also application related encompasses new technologies and tools driven by current research projects local & global industry cooperation Any questions - before student presentation continues

42 42 ASPI Introduction Reklame Min A3 'opdragelse' er kommet rigtig til gavn – vi veksler frem og tilbage mellem applikation, algoritme og arkitektur noejagtig som vi gjorde i de gode gamle dage i VLSI gruppen. Desvaerre faar vi ikke gjort meget ved aritmetikken – syntese vaerktoejerne kommer med meget effektive modulgeneratorer for multipliers, adders etc. – og I den 0.18u teknologi vi arbejder i er de mere end rigeligt hurtige. Saa aritmetikken er mere en del af min baggrund for at forstaa hvad modul generatorerne spytter ud - og hvordan vi bedst udnytter dem. (Og dog - det lysner - jeg skal til at designe en divider for naeste generation IC !-) Uddrag af fra: Jack Andersen

43 43 ASPI Introduction ASPI Home Page, Staff etc Home Page: Secretary: Dorthe Sparre, NJV12 A5-214, Tlf , Staff: Peter Koch, Yannick LeMoullec, Ole Olsen Daniel Lázaro Cuadrado, Anders B. Olsen, Jesper Michael Kristensen, Søren Skovgaard Christensen, Rasmus Abildgren Location: Offices: B1-208, -211, -213, NJV12 A5-207 Lab: NJ Students: A6-108


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