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Appendix Page1 CISC Design By Ralph M. Weber Jr..

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Presentation on theme: "Appendix Page1 CISC Design By Ralph M. Weber Jr.."— Presentation transcript:

1 Appendix Page1 CISC Design By Ralph M. Weber Jr.

2 Appendix Page2 CISC Design Control Signals

3 Appendix Page3 Table 3: Control Signals

4 Appendix Page4 CISC Design Flowchart

5 Appendix Page5 Figure 5: Flowchart 1

6 Appendix Page6 Figure 6: Flowchart 1a

7 Appendix Page7 Figure 7: Flowchart 1b

8 Appendix Page8 CISC Design Console

9 Appendix Page9 Figure 9: CISC Design of Console User Console 32 switches Load Button 48 LED ERROR LED 32 SW LOAD Start Button START 16 switches 16 SW HALT LED Reset Button RESET

10 Appendix Page10 Figure 10: Combinational Logic

11 Appendix Page11 CISC Design Main CPU

12 Appendix Page12 Figure 12: Design of Main Computer MM PC MDR MAR RDWR ACC CU Main Computer Data Paths ALU MDR(OP) MDR(ADR) ACO IR XR MDR SW 32 XR=0 ACC=0ACC>=0 ER 16

13 Appendix Page13 Figure 13: Design of Main Computer MM PC MDR MAR RDWR IR ACC CU Main Computer Control Signals ALU C0 Cn... C0, C5, C6 C3, C11 C1C2 C2,C10 C4 C7, C8, C9, C14, C15, C16, C17, C18, C19, C20 XR C12, C13, C21, C22 C7, C8, C18, C19, C20

14 Appendix Page14 Figure 14: CISC Design of MDR … MDR ID(15)X O(1)O(2)O(3)O(4)O(5)O(6)O(7)O(0) D(4)D(0)D(1)D(2)D(3)D(5)D(7)D(8)D(14)D(9)D(10)D(11)D(12)D(13)D(15)D(6) XI 0 31… O(0)O(7)D(0)……

15 Appendix Page15 Figure 15: MDR Detail Design

16 Appendix Page16 O(6)O(5)O(4)O(3)O(2)O(1)O(0)O(7) Figure 16: CISC Design of Opcode(s) Instruction Opcode(s) ADD01 SUB02 LOAD03 STORE04 JUMP05 JZ06 JPOS07 JXZ08 LDX09 LD0A CLR0B CLX0C SHL0D SHR0E COMP0F NEG10 INC11 DEC12 INX13 DCX14 HALT15

17 Appendix Page17 Figure 17: CISC Design MAR & PC MAR A(n) A(4)A(0)A(1)A(2)A(3)A(5)A(7)A(8)A(14)A(9)A(10)A(11)A(12)A(13)A(15)A(6) 0 15… A(0)… P(n) P(4)P(0)P(1)P(2)P(3)P(5)P(7)P(8)P(14)P(9)P(10)P(11)P(12)P(13)P(15)P(6) 0 15… P(0)… PC

18 Appendix Page18 Figure 18: MAR Detail Design

19 Appendix Page19 Figure 19: PC Detail Design

20 Appendix Page20 Figure 20: CISC Design of XR & ACC XR R(n) 0 15 R(0)… H(n) 0 31 H(0)… ACC

21 Appendix Page21 Figure 21: XR (i=0) Detail Design

22 Appendix Page22 Figure 22: XR (i=30) Detail Design

23 Appendix Page23 Figure 23: XR (i=31) Detail Design

24 Appendix Page24 Figure 24: ACC (i=0) Detail Design

25 Appendix Page25 Figure 25: ACC (i=30) Detail Design

26 Appendix Page26 Figure 26: ACC (i=31) Detail Design

27 Appendix Page27 Figure 27: CISC Design of IR IR I(n) I(4)I(0)I(1)I(2)I(3)I(5)I(7)I(8)I(14)I(9)I(10)I(11)I(12)I(13)I(15)I(6) 0 15… I(0)…

28 Appendix Page28 Figure 28: IR Detail Design

29 Appendix Page29 Figure 29: ALU Detail Design

30 Appendix Page30 Table 30: ALU Tables

31 Appendix Page31 CISC Design Input Equations See text in body of report

32 Appendix Page32 CISC Design Micro Control Unit

33 Appendix Page33 Figure 33: Design of Micro Control Unit EEPROM mPC mMDR RD Micro Control Unit (Data Flow) IR mMDR Control Signal for CPU Cn

34 Appendix Page34 Figure 34: Design of Micro Control Unit EEPROM mPC mMDR RD Micro Control Unit (Control signals) CLK START

35 Appendix Page35 Figure 35: CISC Design of EEPROM Micro Instruction ( Fetch & Execute) EEPROM FETCH LOAD … HALT Indirection Table GO to HALT GO to LOAD GO to …

36 Appendix Page36 Figure 36: CISC Design mPC p(n) 0 8… p(0)… mPC

37 Appendix Page37 Figure 37: mPC Detail Design

38 Appendix Page38 Figure 38: CISC Design mMDR m(n) 0 31… m(0)… mMDR

39 Appendix Page39 Figure 39: mMDR Detail Design

40 Appendix Page40 Figure 40: CISC Design of Control Unit mMDR (External) … Control Unit C(0)I/E 31 0… C(30)

41 Appendix Page41 Table 41: External Instructions See next page

42 Appendix Page42 Figure 42: CISC Design of Control Unit mMDR (Internal) … Control Unit o(7)a(0)I/E 31 0… o(0)a(8)…Not used

43 Appendix Page43 Table 43: Internal Instructions See next page

44 Appendix Page44 CISC Design User Program See next page

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