Lecture 11 Signal Integrity for Nanometer Design Professor Lei He EE 201A, Spring 2004

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Lecture 11 Signal Integrity for Nanometer Design Professor Lei He EE 201A, Spring 2004 http://eda.ee.ucla.edu

Outline  Capacitive noise  Technology trends  Capacitance model and characteristics  Layout optimization  Inductive noise and layout optimization  When inductance become important  Inductance model and characteristics  Layout optimization  Example: SINO algorithm for both Cx and Lx noise  Other noise sources

Interconnect Capacitance CfCf Ca Ca CxCx

Significance of Coupling Capacitance

Delay Variations Due to Coupling Capacitance Cx

Coupling Noise Coupling noise from two adjacent aggressors to the middle victim wire with 2x min. spacing. Rise time is 10% of project clock period. Capacitive coupling depends strongly on both spatial and temporal relations!

Solution to Capacitance Computation  Accurate solution to small structure  Numerical method based on Maxwell’s equations  Raphael RC3, FastCap [Nabors-White, TCAD’91]  Efficient solution to full chip  Using tables or empirical formulas 2.5-D capacitance model [Cong-He-Kahng-et al,DAC’97]2.5-D capacitance model [Cong-He-Kahng-et al,DAC’97]  Capacitance is not simply A/d A: areaA: area d: distanced: distance

Characteristics of Coupling Capacitance  Coupling capacitance virtually exists only between adjacent wires or crossing wires Cx Cx Cx  Capacitance can be pre-computed for a set of (localized) interconnect structures  2D or 2.5D capacitance model

 Noise avoidance technique:  Shield insertion Shield is a wire directly connected to Vdd or Gnd Shield is a wire directly connected to Vdd or Gnd Layout to reduce impact of Cx VddGnds1Gs2s3s4 VddGnds1s2s3s4   Coplanar parallel interconnect structures with pre-routed Vdd and Gnd

Timing Sensitivity  Two nets are considered sensitive if a switching event on signal s 1 happens during a sample time window for s 2 time aggressor Signal levels (V) victim 1 V IH Sampling window error occurs victim 2 no error occurs

 Noise avoidance techniques:  Net ordering (track assignment / net placement) Layout to reduce impact of Cx VddGnds4s1s3s2 VddGnds1s2s3s4   Coplanar parallel interconnect structures with pre-routed Vdd and Gnd

Characteristics of Coupling Capacitance  Coupling capacitance is highly sensitive to spacing  Proper wire sizing and spacing may limit the impact of Cx by changing the ratio Cx/Ctotal E1E1 E1E1 spacing spacing Spacing (nm) Spacing (nm)

Relation between Delay and Noise  T_max = T * ln (1/0.5-v) / ln 2  T_min = T * ln (1/(o.5+v) / ln 2  Typical values VT_max/TT_min/TVT_max/TT_min/T 0.11.320.740.11.320.74 0.151.510.620.151.510.62 0.201.750.520.201.750.52 VIC AGG VOUT w/o XTalk AOUT delay

Noise estimation and filtering  Rule of thumb: Cx/C < thresholdCx/C < threshold  Devgan, ICCAD’97 V < (Rv + Rint / 2) * Cx / (1.25 Tr)V < (Rv + Rint / 2) * Cx / (1.25 Tr) Tr: rising time for the aggressorTr: rising time for the aggressor  Vittal et al, TCAD’99 (more accurate) V = (Rv + Rint / 2) * Cx / {0.63Tr + Ra (Ca + Cx) + Rv (Cv + Cx) + Rint * Cx}V = (Rv + Rint / 2) * Cx / {0.63Tr + Ra (Ca + Cx) + Rv (Cv + Cx) + Rint * Cx}  To reduce Cx impact Increase the driver size of victimIncrease the driver size of victim Decrease the driver size of aggressorDecrease the driver size of aggressor Or bufferingOr buffering Need a global device size solution coupled with Time AnalysisNeed a global device size solution coupled with Time Analysis

Mini-Summary  Capacitive crosstalk is localized  Capacitive crosstalk affects both delay and signal integrity  Capacitive crosstalk can be minimized by Spacing (and wire sizing)Spacing (and wire sizing) Device sizingDevice sizing Net orderingNet ordering ShieldingShielding BufferingBuffering

Outline  Capacitive noise  Technology trends  Capacitance characteristics  Layout optimization  Inductive noise and layout optimization  When inductance become important  Inductance characteristics  Layout optimization  Example: SINO algorithm for both Cx and Lx noise  Other noise sources

Is RC Model still Sufficient?  Interconnect impedance is more than resistance Z  R +j  LZ  R +j  L   1/t r   1/t r  On-chip inductance should be considered When  L becomes comparable to R as we move towards Ghz+ designsWhen  L becomes comparable to R as we move towards Ghz+ designs

Candidates for On-Chip Inductance  Wide clock trees  Skews are different under RLC and RC models  Neighboring signals are disturbed due to large clock di/dt noise  Fast edge rate (~100ps) buses  RC model under-estimates crosstalk  P/G grids (and C4 bumps)  di/dt noise might overweight IR drop

Inductance Minimization  Reference plane wiring layers sandwiched between power planeswiring layers sandwiched between power planes GND plane VDD plane

Inductance Minimization  Coplanar shields Bus signals VDD shield GND shield

Characteristics of Coupling in 18-Bit Bus 0.38V (29%) 2 (b) 0.17V (13%) 5 (c) 0.71V (55%) 0 (a) Noise (% of Vdd) # of Shields (a) (b) (c) Lx coupling between non-adjacent nets is non-trivial Shielding is effective to reduce Lx coupling

Figure of Merit of Inductive Coupling  Inductive coupling coefficient defined as  A formula-based Keff model has been developed  High fidelity between formula and noise voltage [He-Xu, 2000]

Illustration of K eff Computation [XuHe,2000] K eff (i,j) = (f(i) + g(j)) / 2 f(i) = (N i – g l )/(N j – g l ); g(j) = (g r – N j )/(g r -N i )

Inductance Minimization  Staggered inverters/buffers  Differential signals  Nets with opposite switching signals can be placed adjacent to each other Decrease Lx noise at the cost of a higher Cx noiseDecrease Lx noise at the cost of a higher Cx noise Mutual capacitance polarities

Mini-Summary  Inductive crosstalk is globalized  Inductive crosstalk affects both delay and signal integrity  Inductive crosstalk is not sensitive to Spacing (and wire sizing)Spacing (and wire sizing) Net orderingNet ordering  Inductive crosstalk can be minimized by ShieldingShielding BufferingBuffering Ground planeGround plane Differential signalDifferential signal Signal terminationSignal termination

Outline  Capacitive noise  Technology trends  Capacitance model and characteristics  Layout optimization  Inductive noise and layout optimization  When inductance become important  Inductance model and characteristics  Layout optimization  Example: SINO algorithm for both Cx and Lx noise  Other noise sources

 Noise avoidance techniques:  Net ordering (track assignment / net placement)  Shield insertion Shield is a wire directly connected to Vdd or Gnd Shield is a wire directly connected to Vdd or Gnd SINO Problem [He-Lepak, ISPD2K]: Simultaneous Shield Insertion and Net Ordering VddGnds4Gs1s3s2 VddGnds1s2s3s4   Coplanar parallel interconnect structures with pre-routed Vdd and Gnd

SINO/NF Problem  Given: An initial placement P  Find: A new placement P’ via simultaneous shield insertion and net ordering such that:  P’ is capacitive noise free Sensitive nets are not adjacent to each otherSensitive nets are not adjacent to each other  P’ is inductive noise free Sensitive nets do not share a blockSensitive nets do not share a block  P’ has minimal area  Equivalent to one-shield-one-signal  When all nets are sensitive to one another

SINO/NB Problem  Given: An initial placement P  Find: A new placement P’ via simultaneous shield insertion and net ordering such that:  P’ is capacitive noise free  All nets in P’ have inductive noise less than a given value  P’ has minimal area

Properties of SINO Problems  Theorem: The optimal SINO/NF problem is NP-hard  Theorem: The optimal SINO/NB problem is NP-hard  Theorem: The maximum clique in the sensitivity graph is a lower bound on the number of blocks required for all SINO/NF solutions

Sensitivity Graph for SINO Problem  Graph indicating which nets are sensitive to one- another (vertices=nets, edges=nets are sensitive) Sensitivity graph with clique size = 3 One maximal clique

Greedy Shield Insertion  Shield Insertion (SI)  Insert shield when a Cx or Lx violation occurs  Results depend strongly on the initial placement  Net Ordering + Shield Insertion (NO+SI)  First remove Cx coupling by net ordering, then perform shield insertion for Lx  Results depend weakly on the initial placement Separated NO+SI—simultaneous algorithm works better

Graph Coloring SINO (GC)  Our implementation: Greedy-based GC  Can solve with other GC methods as well  Main contributions of SINO-GC:  Provide lower bound measurements for SINO/NF  Comparative reference point

Simulated Annealing SINO (SA)  Cost Function is a weighted sum of:  Number of Cx violations  Number of Lx violations  Inductance Violation Figure (quantizes level of inductive noise)  Area of Placement  Random Moves  Combine two random blocks in placement P  Swap two (arbitrary) random s-wires in P  Move a single random s-wire in P  Insert a shield wire at a random location in P

Quality of SINO/NB Solutions SINO/NFSINO/NB K thresh Graph Coloring Greedy SI NO+SIGCSA Net Sensitivity Rate: 10% 1.03.2 (2.0) 5.02.82.01.8 2.04.21.22.01.0 Net Sensitivity Rate: 30% 1.06.0 (3.8) 13.24.44.23.0 2.013.22.83.82.0 Net Sensitivity Rate: 60% 1.013.6 (8.2) 22.45.48.25.0 2.022.44.08.23.4 Max. clique size in the sensitivity graph # of shields is fewer than lower bound for SINO/NF CPU time is much less than existing net ordering algorithms

Expand to Full-Chip Level  Shield estimation  Crosstalk Modeling (LSK model) @ chip level  Global routing synthesis  Post-routing refinement with optimal crosstalk budgeting

Shielding Estimation  The number of shields for min-area SINO solution is:  Linear with number of nets (N ns )  Quadratic with sensitivities (S i )  Linear with crosstalk bounds (K th,i )  Holds for min-area SINO solutions  Estimation can be used to guide routing synthesis

Shielding Estimation  For known crosstalk bound (K th,i ) but unknown sensitivity rate S i and unknown number of net N ns, the number of shields is  To be used in global routing synthesis  For known S i and N ns but unknown K th,i  To be used in noise budgeting

Shielding Estimation (Cont’d)  In most general case, the number of shields is

Computation of LSK Value  For each sink, LSK value is   Sum over the path from source to sink  l j : length of the region j where net i is routed  K i j : sum of inductive coupling coefficients for net i in region j Region H1 Region H3 Net i Region H2

Fidelity of LSK Model  For SINO solutions, higher LSK values  higher SPICE-computed noise using detailed RLC circuits

Converting LSK Value to Noise Voltage  Table building  Consider SINO solution of parallel interconnect buses (i.e., two-pin nets)  Compute and store both LSK values and noise voltages via SPICE simulation  Table lookup (either two-pin or multi-pin nets)  Linear interpolation and extrapolation

Verification of LSK Model  Errors less than 15% for SINO solutions to two-pin nets  Errors less than 20% for SINO solutions to multi-pin nets

GSINO Problem Formulation  Given  Pin locations of each net  RLC crosstalk bound for each sink  Decide  Rectilinear Steiner tree for each net  SINO solution within each routing region  Such that  RLC crosstalk constraint is satisfied for each sink  Wire length is minimized  Chip area is minimized

Overall GSINO/LD Algorithm  GSINO is NP-hard  Sub-problem SINO is NP-hard  High-quality solution via three-phase GSINO/LD algorithm  Phase I: Global routing with linear distribution of crosstalk bounds  Phase II: SINO within each region Developed in [He-Lepak, ISPD’00]Developed in [He-Lepak, ISPD’00]  Phase III: post-routing refinement (RF)

Algorithm Phase I  Routing topology generation  L and Z shape routes within bounding box of all pins  Leads to fixed path length from source to each sink  Crosstalk bound distribution  Linear distribution from source to each sink for fixed length  More sophisticated solution presented later on

Algorithm Phase I (Cont’d)  Routing algorithm: Iterative deletion (ID) [Cong-Preas, Integration’92]  Start with net connection graph (completed graph)  Iteratively delete the edge with the largest weight  Until graph becomes a tree α * f (wire_length) + β * density (R i ) + γ * overflow (R i )  Density = signal nets + estimated shields (via formula)  Shielding area is reserved  Shielding area is minimized as sensitive nets are automatically distributed to different regions  Alternative global routing algorithm may be applied

Algorithm Phase III  Phase III: post-SINO refinement (RF)  Eliminate remaining but limited RLC noise violations Start with most severe crosstalk-violating netStart with most severe crosstalk-violating net Decrease noise bound to allow one more shield in the least congested region using the formulaDecrease noise bound to allow one more shield in the least congested region using the formula Until no crosstalk violationsUntil no crosstalk violations  Reduce routing congestion Start with most congested regionStart with most congested region Increase noise bound to remove one shield in the region using the formulaIncrease noise bound to remove one shield in the region using the formula Until new SINO solution without crosstalk violationUntil new SINO solution without crosstalk violation

Experiment Settings  Comparison among  ID+NO ID: ID-based global routing without considering shielding in the weight functionID: ID-based global routing without considering shielding in the weight function NO: net ordering to eliminate as much capacitive coupling as possibleNO: net ordering to eliminate as much capacitive coupling as possible  iSINO/LD = ID + SINO + RF (best alternative)  GSINO/LD  ITRS 0.10um technology Vdd1.05V Load capacitance 60fF Frequency3GHz Wire width 1.0μm Input rising time 33ps Wire thickness 1.1μm Driver resistance 150Ω Wire spacing 0.8μm

Benchmark Circuits  Large scale industrial benchmark circuits  Placement done by DRAGON [Wang et al, ICCAD’2K]  Uniform crosstalk constraints 0.15V (15% of Vdd) Number of nets Number of regions Number of pins Region’s capacity Regions physical size (μm * μm) ibm0113056 64 * 64=4096 45815 V:12 H:14 25 * 30 ibm0219291 80 * 64=5120 79033 V:22 H:34 40 * 65 ibm0326104 80 * 64=5120 80193 V:20 H:30 40 * 60 ibm0431328 96 * 64=6144 94756 V:20 H:32 40 * 60 ibm0529647 128 * 64=8192 127509 V:42 H:63 80 * 115 ibm0634395 128 * 64=8192 125880 V:20 H:33 40 * 60

Number of Crosstalk-violating Nets  Up to 25% of nets may have crosstalk violations in ID+NO  No crosstalk violations for iSINO and GSINO ID+NOiSINO-RFiSINOGSINO-RFGSINO Sensitivity rate = 30% ibm0119821770790 ibm02337032101480 ibm03508536501960 ibm04539254503020 ibm05452855202090 ibm06495139801630 Sensitivity rate = 50% ibm01269527201130 ibm02438644801850 ibm03623766303270 ibm04620189103460 ibm05734891203620 ibm06675260502590

Expand to Full Chip  Crosstalk Modeling  Global routing synthesis  Post-GR refinement with optimal crosstalk budgeting  iSINO formulations  iSINO/LP algorithm  Experiment results  Conclusions

iSINO Formulation  Given:  Global routing solution and crosstalk constraints at sinks  Find:  A partition of crosstalk budget among routing regions and a SINO solution for each region  Such that  The crosstalk constraint is satisfied, and the routing area is minimized

Overall Algorithm of iSINO  Phase I : noise budgeting for given global routing  CB/1D, CB/2D, CB/2D-p  Phase II: SINO within each region  Same as in GSINO  Phase III: post-routing refinement  Same as in GSINO

Crosstalk Budgeting for One-dimension Routing (CB/1D Problem)  Given:  One-dimension routing solution  Find:  Partitioning of crosstalk bounds  Such that  The maximum height is minimized blockage source sink h max Minimize h max

CB/1D Problem formulation blockage source sink h max

 Given  two-dimension routing solution  Find  partition crosstalk bounds among all routing regions  Such that  the weighted sum of maximum height and width is minimized. Crosstalk Budgeting for Pseudo Two- Dimension Routing (CB/2D-p problem) blockage sink i1 sink i2 source i sink j1 source j h max w max Minimize  *w max +  *h max

CB/2D-p problem formulation blockage sink i1 sink i2 source i sink j1 source j h max w max

 Given  two-dimension routing solution  Find  partition crosstalk bounds among all routing regions  Such that  the total chip area is minimized. Crosstalk Budgeting for Two-Dimension Routing (CB/2D problem) Minimize: w max * h max blockage sink i1 sink i2 source i sink j1 source j h max w max

CB/2D problem formulation blockage sink i1 sink i2 source i sink j1 source j h max w max

Main Theorem  CB/1D and CB/2D-p problem are linear programming (LP) problem  all constraints and the objective are linear  CB/2D problem are non-linear programming (NLP) problem  The objective is nonlinear (but all constraints are linear though)

Conclusions and Further Study  LP-based noise budgeting reduce routing area by 5.71%  Details see reading assignment  Multi-level routing may be used to reduce runtime of iterative deletion and consider integrity for both power and signal nets  Student presentation  Detailed modeling for capacitive noise  Bottom-up model  2-  model

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