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WEBENCH Power Designer/Architect

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Presentation on theme: "WEBENCH Power Designer/Architect"— Presentation transcript:

1 WEBENCH Power Designer/Architect

2 Power Architect & FPGAs
The WEBENCH Tool Suite Altera PowerPlay Power Architect & FPGAs FPGA/Power Architect WEBENCH Visualizer WEBENCH Power Designer 2 2 2 2

3 Beginning To End: Design And Prototyping
1. Choose a Part 2. Create a Design 3. Analyze a Design 4. Build It! Enter Specifications Custom Prototype Kit Overnight Optimize for Footprint and Efficiency, Use Graphs to Visualize Design Generate Schematic/ Electrical Analysis The WEBENCH Design Environment is an end to end prototyping system with 4 simple steps: The user enters design parameters and WEBENCH presents appropriate solutions. After the user choose a part, the WEBENCH Design Environment creates a design and provides the user with optimization capability. The user can also use the WEBENCH Design Environment simulators to fine tune the design. Finally a custom prototype kit is available overnight for parts with the Build It feature. Select Part Prototype Generate Layout/ Thermal Analysis 3 3 3

4 Two Ways to Access WEBENCH® Designer
Use the entry panel on OR Go to the product folder for a part Different ways to access WEBENCH Designer. User enters the input voltage range, output voltage and load current. Then hit “Start Design” button . 4 4 4

5 WEBENCH Navigation Navigation Icons WEBENCH Tools: Power LED
LED Architect Power Architect FPGA Power Architect Once inside the WEBENCH Power Designer tool, the user can navigate between steps using the icons at the top of the page. Clicking on the New icon takes the user to the main entry panel where other WEBENCH Power tools can be accessed. 5 5

6 BOM/Change Components
Create and View Design Dashboard Graphs Schematic Optimization Operating values BOM Reporting Simulation Controls Op Vals Charts Schematic Optimization The main design dashboard gives the user an overview of the design. BOM/Change Components Build It® & Report Inputs Op Vals 6 6 6

7 Schematic – Buck Converter
Components: Input Capacitor Regulator with integrated FET Inductor Catch Diode Output Capacitor Feedback Network Feature Controls Current Path with Switch On Current Path with Switch Off This is a schematic of a buck asynchronous voltage regulator circuit. It shows the current path with the switch on and also with the switch off. From this we can determine the primary contributors to power dissipation in the circuit. Input Load

8 Visualize Behavior – Power Dissipation
Efficiency = Pout / Pin Pin = Vout * Iout + Pdiss Diode: Isw*Vf *(1-DutyC) Cout: ICoutRMS2 * ESR Efficiency includes the losses from all the components. The major contributors are the regulator/switch and the catch diode depending on the duty cycle. Low duty cycle designs have higher power dissipation in the diode and high duty cycle designs have higher power dissipation in the regulator. Graphs of power dissipation vs current help to visualize the losses Switch: DC: IswRMS2 * Rsw * DutyC AC: ½ * Vin * Isw * (Trise + Tfall)/Tsw Quiescent: Iq * Vin Inductor: ILRMS2 * DCR Cin: ICinRMS2 * ESR

9 FET Selection: AC Loss PswAC = ½ * Vdsoff * Idson * (trise + tfall)/Tsw Regions of power loss (V*I) Vsw Miller Plateau Miller Plateau Vdriver Vth Vth The AC loss occurs during the transition between the switch being on and off. This diagram shows the behavior of the FET during the transition from off to on then from on to off. The highlighted areas show regions of AC power loss. Isw Vg Vsw = -Vds Switch Off On Off Tfall Trise 9

10 FET Selection: AC Loss PswAC = ½ * Vdsoff * Idson * (trise + tfall)/Tsw High Freq = High Loss Low Freq = Low Loss Regions of power loss (V*I) Vsw Miller Plateau Miller Plateau Vdriver The % of the switching period that is spent in the transition regions is greater for higher switching frequencies. Thus, higher switching frequency means greater AC switching loss as is shown in the diagram in the upper left. Lowering the switching frequency lowers the losses as is shown in the upper right. AN-1628 has more details on this (http://www.national.com/an/AN/AN-1628.pdf). Vth Vth Isw Vg Vsw = -Vds Switch Off On Off Trise Tfall

11 How To Reduce FET Power Loss
Choose a FET with low RdsOn Choose a FET with low capacitance Lower the switching frequency BUT Lowering frequency affects the inductor selection We want to keep the inductor ripple current constant Because this changes the peak switch current and the Vout ripple

12 Inductor Current vs Switch Voltage
Voltage is applied to the inductor at the switch node minus the voltage at the output. This cause the current to rise in the inductor. When the switch is turned off, the inductor current goes down.

13 Inductor Ripple Current
On Time Voltage applied dI = (1/L)*V*dt Inductor Ripple Current (also determines peak switch current and Vout ripple) The peak inductor current (and peak switch current) is a function of the average output current and the inductor ripple current. The peak inductor current is: ILaverage + 1/2 ILpp (the inductor ripple current) The average inductor current is: For Buck: ILaverage = Iout For Boost: ILaverage = Iout/(1-DC) where DC = duty cycle DC = (Vout-Vin+Vdiode+ILavg*DCR)/(Vout - Vswitch + Vdiode) Higher DCR means higher duty cycle and higher average inductor current The inductor ripple current is determined by the basic inductor equation: V = L dI/dt di = V/L dt Peak to peak inductor current (inductor ripple current) = Voltage applied across the inductor/L * time during which voltage is applied to the inductor. When the switch is closed we have: For Buck: ILpp = (Vin - Vswitchingloss - ILavg*DCR - Vout)/L * Ton For Boost: ILpp = (Vin - Vswitchingloss - ILavg*DCR)/L * Ton Since the on time is: Ton = duty cycle/switching frequency We see that the on time is inversely proportional to the switching frequency. So the lower the switching frequency, the higher the inductor ripple current and thus peak inductor current.

14 Inductor Selection – Lower Frequency
Time Higher frequency: Voltage applied dI = (1/L)*V*dt Inductor Ripple Current (also determines peak switch current and Vout ripple) Lower Frequency = Increased On Time = Increased Inductor Ripple Current = Increased Peak Switch Current and Increased Vout Ripple Lower frequency: Lower frequency = longer ON time means more inductor ripple current and higher peak current and Vout ripple for a given inductance. If L is kept constant, ILpp increases

15 Inductor Selection – Raise Inductance
Time Higher frequency: Voltage applied dI = (1/L)*V*dt Inductor Ripple Current (also determines peak switch current and Vout ripple) Lower frequency with higher inductance: Lower frequency: So we need to raise the inductance to keep the ripple current constant. This typically requires more turns/more wire which increases the size of the inductor. More wire also tends to increase the DCR (DC resistance) which leads to more power dissipation. Note: When creating a design, a rule of thumb for sizing an inductor is to try for +/- 15% inductor ripple current. This depends on the topology and the application and there can be a lot of variation (>100% ripple is desirable in some cases, particularly if the current is low. The circuit would then be running in discontinuous mode) If L is kept constant, ILpp increases So we need to increase L

16 Effect Of Lower Frequency On Inductor
If we keep the inductor ripple current constant by increasing the inductance: The inductor gets larger (more turns) The inductor power dissipation goes up (longer wire)

17 Optimization – Efficiency vs Footprint
Here is a summary of optimizations done on a buck controller design. In general, at a high optimization number, the frequency is lower, which causes lower AC switching losses. However, it also requires more inductance to limit the ripple current. This results in a larger inductor due to the higher number of turns required and larger overall footprint. At the lower optimization settings, the opposite is true. Higher frequency requires less inductance and thus, results in smaller inductors and lower overall footprint. There are additional factors being weighted in the selection process including parasitic resistance (ESR, DCR), component cost and availability. Left side: Higher frequency Smaller footprint Right side: Lower frequency Lower resistance

18 Optimization Summary To get high efficiency To get small footprint
Decrease frequency to reduce AC losses Choose components with low resistance To get small footprint Increase frequency to reduce inductor size Choose components with small footprint Cost These parameters are at odds with each other and need to be balanced for a designer’s needs Tools are available to visualize tradeoffs and make it easier to get to the best solution for your design requirements

19 Power Architect & FPGAs
The WEBENCH Tool Suite Power Architect & FPGAs WEBENCH Visualizer WEBENCH Power Designer 19 19 19 19

20 WEBENCH Visualizer- Calculates 50 Designs In 2 Seconds
Recommended Solutions For this design criteria (Vin: 14-22V, Vout: 3.3V, Iout: 2A) the WEBENCH Visualizer calculates 46 possible solutions and ranks them in recommended order. The results are presented in a table and also in a graph. The user can select which parameters to plot in the graph such as BOM Cost, Efficiency, and Footprint, among other things. These are calculated for each design independently and in real time. The user can change the desired optimization by using the knob in the upper left corner. Optimization 1 corresponds to low footprint, optimization 3 goes for low BOM cost and optimization 5 emphasizes high efficiency. The user can also filter the results using slider controls and also using checkboxes for different features. Charts 20 20 20

21 Calculated BOM Footprint, BOM Cost and Efficiency
Footprint vs Cost vs Efficiency The BOM footprint, BOM cost and efficiency are calculated for each design in the list in real time. This allows the user to instantly compare critical design parameters which would otherwise take many hours or days to compute. 21 21 21

22 Graphical Plot Gives At A Glance TradeOffs
Click on square to resize the plot to full screen size Hover to see details Click and drag to zoom Change plot parameters To view the results graphically, use the chart in the lower left corner. Clicking on the resize box makes the chart go to full screen. The default axes for the graph are footprint on the Y axis, efficiency on the X axis and price for the radius of each point. Hovering over a point will show details about the solution including a thumbnail of the schematic, BOM, component manufacturers and operating values. Bubble Size = BOM Price 22 22 22

23 Why Are The Solutions Different?
The solutions are different because there are different types of regulators and topologies presented together. Typically, synchronous controllers give the highest efficiency, but they can be difficult to use and may have larger footprint. Asynchronous parts with on board FETs are easier to use and may have smaller footprint, but can have lower efficiency. 23 23

24 Give The Customers What They Want: Best Efficiency, Footprint and BOM Cost
Default Setting: LM22676, 80%, 411mm2, $2.88 Smallest Footprint: LM25011, 75%, 297mm2, $2.47 Highest Efficiency: LM3150, 94%, 1320mm2, $6.77 Comparing different designs up front, achieves better results than optimizing 1 part after creating a design Comparing the 3 optimizations, it can be seen that the results are quite different with the different solutions that are recommended. The user can decide which is appropriate for the design goals. 24 24 24

25 Power Architect & FPGA Architect
The WEBENCH Tool Suite Power Architect & FPGA Architect WEBENCH Visualizer WEBENCH Power Designer 25 25 25 25

26 Design This Power Supply In Seconds?
Many Loads, Many Supplies Core Supply FPGA IO Vcca Flash SDRAM CCD PLL Motor Control Miscellaneous Lets go over a real example of a complex PC board design. National has a development platform for FPGA-based motor control including industrial communication interfaces and current drive management. The core design includes FPGAs, processors, Flash and DDR memories, communications and JTAG test interfaces, and motor driver and user interface connectors. This board has 9 different loads with differing voltages and currents. The work to create the entire power architecture for a board like this can take significant time and development. The first task is figuring out which loads can be grouped together. Next the designer needs to determine which intermediate rails are necessary and finally which power supply solutions are appropriate. Add to this the desire to balance high efficiency, small footprint and low cost and the challenge becomes significant. If done by hand, this can take days or weeks. This is what WEBENCH® FPGA Architect now makes possible, fast, and easy. 9 Loads and 5 Voltages 26 26 26

27 Minutes, right? With Confidence?
Why Do Designers Use Reference Designs So Frequently For Complex FPGAs? Cyclone IV GX - EP4CGX150 User guide: 463 pages, 10MB 20-30 pages of power details Spartan-6 - XC6SLX100T 40+ separate reference guides and datasheets: ~2000 pages, 90MB 15 pages critical for power details Each specification includes challenging requirements and exceptions Voltage, current, ripple, frequency, accuracy, soft start, supply isolation, and pin specific limitations Every complete system has additional loads beyond the FPGA loads, adding more to the complexity Minutes, right? With Confidence? 27 27

28 WEBENCH® FPGA Power Architect
Select Device From List Add FPGA Configure Loads Now, that WEBENCH has captured the requirements for the individual power rails for your selected FPGA, we attempt to make the creation of your optimized power solution as easy as possible. In the WEBENCH FPGA Power Architect interface, the user selects the preferred vendor FPGA from the list. That selection populates the signal constraints and voltage and current rail template for that array. The user can further configure the selections by updating the pull downs or by unselecting an I/O Bank for example. The supply rails that remain when the user cilcks on the green Add Loads button will be added to the next load configuration step. 28

29 Get FPGA Load Current From Vendor Estimation Spreadsheet: Xilinx
Spreadsheet calculates the current When the user designs and configures their FPGA using the vendor’s power budget estimation spreadsheet, the key current demands will be shown in the Power Supply Current columns. 29 29 29 29 29 29

30 Update Load Current Into Preconfigured FPGA Dependency Template
Voltage, Current, and Special Requirements Included For: Max Voltage Ripple Isolated Supplies Soft Start Post Supply Filters LDO Preferred Add All Of Your Own Additional System Loads Next The FPGA loads are preconfigured to have the correct power supply requirements including voltage ripple, post supply filters, LDO preferred and soft start. The user can change any of the entries and also change voltages and currents, if desired. Additional supplies can also be added here. 30 30 30 30 30 30

31 Each Architecture Is Tuned With The WEBENCH Optimizer, Now For Systems
Optimizer Dial 8000 Relative System Cost As the optimizer dial is turned, new sets of system power architectures are added to the ball graph which are designed with the component selection algorithms tuned to the optimizer dial setting. For example, when you turn the dial to smallest footprint, every component selection is for the smallest part. Size 2000 76% System Efficiency 92% 31 31 31 31 31

32 WEBENCH FPGA Power Architect Selects The Best Solutions For Every Rail
Intermediate Rail (12V) Supply 2 (1.25V) Supply 3 (3.3V) Loads This system architecture has an intermediate rail and 4 point of load supplies for the loads. FPGA Power Architect will attempt many options for the intermediate rail values and then optimize the selection of all of the individual power supply loads based on the best choice for each rail. Each supply may have 50 or more solutions. This graphic shows the Visualizer output for each supply but only the best in each case will be presented back to the user. FPGA Power Architect uses the Visualizer algorithms to determine the best supply for each node in the system. Thus, hundreds of different solutions are weighed to achieve the final optimized supply. Supply 4 (1.8V) Supply 5 (2.5V) 32 32

33 Presenting The User With The Intermediate Rail Options And Performance Trade-Offs
Intermediate Rail Options Can Be Reviewed & Compared Quickly 12V 3V 5V No I-Rail Each power architecture had different intermediate rails and components. This results in different size, efficiency, and total cost. One of the options shown has no intermediate rail at all. Others have one, two or three intermediate rails at different voltages. Each case results in a different tradeoff between small footprint, high efficiency and low BOM cost. Lowest Cost 12V 12V 23V 5V Smallest Footprint Highest Efficiency 33 33 33 33 33

34 Analyze Performance, Cost and Footprint for Selected Architecture
Go Click on Each Supply To Display Detail On the View/Edit page, there are pie charts which allow the user to examine the contributions of each supply in the system to the power dissipation, BOM price and footprint. By clicking on a supply, the user can get more details. The user can also click on the Alternate Solutions tab to choose another power supply solution, if desired. In this way the user can determine if one of the supplies is making a large contribution to a problem and take corrective action. For example, if one supply is responsible for most of the footprint, the user can select another power supply solution with smaller footprint, if it is available. The user can also edit the power tree architecture by clicking on the edit button. Next click on the Create Project Design button to save the project and go to the next step. 34 34 34 34 34

35 WEBENCH® FPGA Architect Leverages The WEBENCH Dashboard
Click on Each Supply To Analyze Design Once the project is created and saved, it is opened in the WEBENCH environment. The system block diagram appears on the left. Each power supply design can be accessed by clicking on the appropriate block. 35 35 35 35 35

36 Advanced Tools Are Available For Further Exploration
Share Design Optimizer System Summary Simulation Optimization Graphs Charts Drive Circuits All of the advanced tools of WEBENCH® Power Designer are available to interrogate your design. Thus the designer can use WEBENCH features including viewing and changing the BOM, viewing charts of critical operating values such as efficiency vs load current, conducting electrical simulation, conducting thermal simulation (if available) and getting a prototype kit using the WEBENCH Build It feature (if available). In the upper left is a summary of the system parameters such as the system efficiency, system BOM cost and system footprint. Bill of Materials Prototyping System Op Vals Power Topology & Design Reports 36

37 Complete FPGA Power Supply Design Reporting – Automatic Generation
Your Design From The Top: Inputs, Supplies, Schematics, BOMs Every time you adjust any of the WEBENCH® FPGA Power Architect designs, the documentation is updated and completely synchronized. The complete design report is dynamically created and can be printed or exported at any time. 37 37

38 Hands On Exercise What is the system with the: Design Problem: Goals:
Source: 18 – 32V Loads: LCD Panel: 3.3V, 0.2A Flash Memory: 1.8V, .05A Freescale QorIQ P2020 Avdd: 1.05V, 1A BVdd: 1.8V, .06A Cvdd: 1.8V, .02A Gvdd: 1.5V, .9A LVdd: 2.5V, .1A OVdd: 3.3V, .01A SVdd: 1.05V, .4A Vdd: 1.05V, 5.6A XVdd: 1.05V, .4A What is the system with the: Smallest footprint Highest efficiency Lowest cost 38 38 38

39 Summary WEBENCH Visualizer WEBENCH Power Architect
View up to 50 designs at a time to get the best solution for a single power supply Each design optimized for efficiency, cost and size WEBENCH Power Architect System level designs for complex multiple load applications Provides different rail architectures Each system optimized for efficiency, cost and size WEBENCH FPGA/Processor Power Designer Preconfigured FPGA and processor loads including noise/filter requirements WEBENCH saves you time!

40 Thank You! Try WEBENCH® FPGA Power Architect yourself:
LED Architect: Jeff Perry 40


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