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Lab 13 : Binary Counter Systems: Slide 2 Slide 3 Three stage ripple counter. Down Counters. Slide 4 Up/Down Counters. Slide 5 Altera 4count Symbol.

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Presentation on theme: "Lab 13 : Binary Counter Systems: Slide 2 Slide 3 Three stage ripple counter. Down Counters. Slide 4 Up/Down Counters. Slide 5 Altera 4count Symbol."— Presentation transcript:

1 Lab 13 : Binary Counter Systems: Slide 2 Slide 3 Three stage ripple counter. Down Counters. Slide 4 Up/Down Counters. Slide 5 Altera 4count Symbol.

2 JK flip flops connected in the toggle mode can be connected together to create a binary counter system. Start with one JK flip flop, apply a clock waveform and sketch the Q output response. Assume PRE and Clr has been disabled (=1) on all flip flops. Lab 13 : Three Stage Ripple counter : J K Qa >Clk 1 1 Input Qa will toggle on each negative edge of the input clock. Qa Connect a second stage to output Qa. J K Qb >Clk 1 1 Qb will toggle on each negative edge of Qa. Qb Connect a third stage to output Qb.Qc will toggle on each negative edge of Qb. J K Qc >Clk 1 1 Qc Label the input clock pulses from 0 to 7 and place the counter response in a table. 000 QcQbQaIn Connect the flip flop outputs to 3 LED’s and you will see a binary count sequence from 0 … to … 7. The speed at which the counter counts is controlled by the input clock. 1 PPS input clock will display the 0 to 7 count sequence on the LED’s in 8 seconds. Each count state would last 1 sec. If the clock input was 1000 PPS then all 3 LED’s would appear to be constantly on at the same time. A count cycle would take 8milliSec. Too fast to be visible on the 3 LED’s. The table is called a COUNT state table. The counter is called a MOD 8 counter because it has 8 different count states. The counter restarts at 0, 0, 0 after clock input 7. MOD is short for the word MODULUS. Slide #2

3 Lab 13: Down Counters : To make a counter count backwards all you need to do is to connect the Q to the Clk of the next flip flop. J K Qa >Clk 1 1 J K Qb >Clk 1 1 J K Qc >Clk 1 1 Qa Input Qa toggles on every negative edge of the input clock. Qb toggles on every negative edge of Qa. QaA negative edge on Qa is the same as the positive edge Qa. Qb Qc toggles on every negative edge of Qb. Which is the same as the positive edge of Qb. Qc 000 QbQaIn If you place the count states in a table you can see the down count sequence. Slide #3

4 Qa1Qb Lab 13: Up/Down Counter : This system combines the features of both an up and a down counter. The system has a count direction control input to select up counting or down counting. When the control input is low, the top AND gates will pass the logic levels from the Q outputs. The bottom AND gates output 0. The OR gate outputs a Q1+0 = Q. This connects Q to clock and the counter counts up or forward. 00 When the control input is high, the bottom AND gates pass the logic levels from the Q outputs. Qa1Qb1 The top AND gates output 0. The OR gate outputs a Q1+0 = Q. This connects Q to clock and the counter counts down or backwards. 0 0 Slide #4 J K Qa >Clk 1 1 J K Qb >Clk 1 1 J K Qc >Clk 1 1 Up/Down

5 Lab 13: Altera 4Count Symbol: The Altera 4count symbol is a 4-bit counter system. Apply a pulse waveform to the positive edge triggered clock input and it counts from 0 to 15. LDN A B C D CIN DNUP CLRN CLK SETN QA QB QC QD COUT 4count Synchronous Load: LDN and ABCD and Clock: LDN=0 loads a number into Qa, Qb, Qc, Qd from A, B, C, D on positive edge of clock. LDN=1 disables the load feature. Clock is used for counting. The animation will demonstrate how to load the number 6 into the counter Step 1: Assert load and place number at inputs Step 2: Assert Clock Asynchronous Load: SETN and ABCD: SETN=0 loads a number into Qa, Qb, Qc, Qd from A, B, C, D immediately. The clock is not required. SETN =1 disables the load feature. Clock is used for counting. The animation will demonstrate how to load the number 6 into the counter Step 1: Place number at inputs Step 2: Assert SETN 0 Asynchronous Clear: CLRN: CLRN=0 resets (clears) Qa=Qb=Qc=Qd =0. Clock not required CLRN =1 disables the clear feature. Clock is used for counting. Count Direction: DNUP: DNUP=0 Counter counts forward or up (0,1,2…). DNUP=1 Counter counts backwards or down (15,14,13…). The animation will demonstrate an up count sequence to 4 and then a down count sequence back to 0. The count sequence can be reversed at any time. CIN and COUT: Carry in and Carry out are used to cascade counter symbols. Cascading will be explained in an upcoming lab. Assert CLRN Step 1: Disable load and clear inputs Step 2: Enable up counting Step 3: Apply 4 clock pulses Step 4: Enable down counting Step 5: Apply 4 clock pulses Altera Default Values: Altera connects LDN, SETN, CLRN, DNUP and CIN to 1 if they are left unconnected in a drawing. These are called default values. The default values will make the counter count down and disable the loading and clearing functions. Slide #5


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