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1 Real-World Instruction Set Architectures Focus on IA-32 Course website:

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1 1 Real-World Instruction Set Architectures Focus on IA-32 http://www.pds.ewi.tudelft.nl/~iosup/Courses/2012_ti1400_5.ppt Course website: http://www.pds.ewi.tudelft.nl/~iosup/Courses/2012_ti1400_results.htm

2 TU-Delft TI1400/12-PDS 2 IA family IA (Intel Architecture) is a family of processors Each processor—same architecture, but different organization -same instruction set -different performance 32-bit memory addresses and variable length instructions Very large instruction set (not RISC) 1982 1985 1989 1993

3 TU-Delft TI1400/12-PDS 3 Floorplan IA-32

4 TU-Delft TI1400/12-PDS 4 Other Example: PowerPC Floating-point unit Integer unit Instruction unit instructions Cache main memory

5 TU-Delft TI1400/12-PDS 5 Floorplan PowerPC

6 TU-Delft TI1400/12-PDS 6 FPU Data Cache Instr. Cache Registers MMU Load/Store Unit Floorplan PowerPC

7 TU-Delft TI1400/12-PDS 7 IA-32 1.Introduction 2.Memory Layout 3.Registers 4.Instructions 5.Examples of Assembler Code for IA-32 6.Subroutines

8 TU-Delft TI1400/12-PDS 8 Memory Memory is byte addressable Doublewords can start at any byte location Data Operands are 8 or 32 bits wide Mode is little-endian scheme (vs big-endian PowerPC)

9 TU-Delft TI1400/12-PDS 9 Addressable data units byte 3byte 0 310Bit Byte Doubleword 0

10 TU-Delft TI1400/12-PDS 10 IA-32 1.Introduction 2.Memory Layout 3.Registers 4.Instructions 5.Examples of Assembler Code for IA-32 6.Subroutines

11 TU-Delft TI1400/12-PDS 11 IA register structure FP0 FP7 floating - point registers R0 R7 general- purpose registers

12 TU-Delft TI1400/12-PDS 12 Register Naming R0EAX R1EBX R2ECX R3EDX R4 ESP R5 EBP R6 ESI R7 EDI EIP EFLAGS Data registers Pointer registers Index registers Instruction Pointer Status Register ALAH AX

13 TU-Delft TI1400/12-PDS 13 Status Register OFIF 31131211 0 Status Register CFTFSFZF 6789 CFCarry ZFZero SFSign IOPLI/O privilege level OFOverflow IFInterrupt enable IOPL

14 TU-Delft TI1400/12-PDS 14 Special registers Code Segment CS Stack Segment SS DS ES FS GS Data Segments

15 TU-Delft TI1400/12-PDS 15 IA-32 1.Introduction 2.Memory Layout 3.Registers 4.Instructions 5.Examples of Assembler Code for IA-32 6.Subroutines

16 TU-Delft TI1400/12-PDS 16 Instructions Variable length instructions 1-12 bytes Five type of instructions -Copy instructions (MOV) -Arithmetic and logic instructions -Flow control -Processor control instructions -I/O instructions Format: INSTR Rdst,Rsrc

17 TU-Delft TI1400/12-PDS 17 Instruction Format OpcodeAddressingDisplacementImmediate 1 or 2 bytes 1 or 4 bytes variable opcode length

18 TU-Delft TI1400/12-PDS 18 Addressing modes Many addressing modes: 1.Immediatevalue 2.DirectM(value) 3.Register[reg] 4.Register IndirectM([reg]) 5.Base with displacementM([reg]) +Disp 6.Index with displacementM([reg]  S +Disp) 7.Base with indexM([reg1]+[reg2]  S) 8.Base with index and M([reg1]+[reg2]  S+Disp) displacement S=1,2,4 or 8Disp= 8 or 32-bit signed number Q CISC or RISC? Q Why both 5 and 6?

19 TU-Delft TI1400/12-PDS 19 Immediate and Direct Immediate MOV EAX, 25 [EAX]  #25 MOV EAX, 3FA00H [EAX]  # 3FA00H Direct MOV EAX, loc [EAX]  M(loc) or MOV EAX, [loc] [EAX]  M(loc)

20 TU-Delft TI1400/12-PDS 20 Register indirect Register MOV EBX,OFFSET loc [EBX]  #loc or LEA EBX,loc [EBX]  #loc Register indirect MOV EAX,[EBX] [EAX]  M(EBX) and MOV [EBX], 10 [EBX]  10 MOV DWORD PTR [EBX], 10 [EBX]  10 Q Why DWORD PTR?

21 TU-Delft TI1400/12-PDS 21 Base with Index and Displacement MOV EAX,[EBP+ESI*4+200] EAX  M([EBP] + [ESI]*4 + #200) Operand 1000 40 EBP ESI 1000 1200 1360

22 TU-Delft TI1400/12-PDS 22 Arithmetic instructions May have one or two operands ADD dst,scr meaning [dst]  [dst] + [src]

23 TU-Delft TI1400/12-PDS 23 Compare Used to compare values and leave register contents unchanged CMPdst, src[dst] - [src]

24 TU-Delft TI1400/12-PDS 24 Flow control Two basic branch instructions: JMP[loc]Branch unconditionally JG, JZ, JS, etc Branch if condition is satisfied

25 TU-Delft TI1400/12-PDS 25 IA-32 1.Introduction 2.Memory Layout 3.Registers 4.Instructions 5.Examples of Assembler Code for IA-32 6.Subroutines

26 TU-Delft TI1400/12-PDS 26 Summation example Java code int[] listarray = new list[n]; int sum=0; for(index=n-1, index>=0, index--){ sum += list[index]; }

27 TU-Delft TI1400/12-PDS 27 Summation example Assembler code, Version 1 [1/4] LEAEBX, NUM1[EBX]  #NUM1 MOVECX, N[EXC]  M(N) MOVEAX, 0[EAX]  #0 MOVEDI, 0[EDI]  #0 L:ADDEAX, [EBX+EDI*4]Add next number to EAX INCEDI[EDI]  [EDI] +1 DECECX[ECX]  [ECX] -1 JGLBranch if [ECX]>0 MOVSUM, EAXM(SUM)  [EAX]

28 TU-Delft TI1400/12-PDS 28 Summation example Assembler code, Version 1 [2/4] LEAEBX, NUM1[EBX]  #NUM1 MOVECX, N[EXC]  M(N) MOVEAX, 0[EAX]  #0 MOVEDI, 0[EDI]  #0 L:ADDEAX, [EBX+EDI*4]Add next number to EAX INCEDI[EDI]  [EDI] +1 DECECX[ECX]  [ECX] -1 JGLBranch if [ECX]>0 MOVSUM, EAXM(SUM)  [EAX]

29 TU-Delft TI1400/12-PDS 29 Summation example Assembler code, Version 1 [3/4] LEAEBX, NUM1[EBX]  #NUM1 MOVECX, N[EXC]  M(N) MOVEAX, 0[EAX]  #0 MOVEDI, 0[EDI]  #0 L:ADDEAX, [EBX+EDI*4]Add next number to EAX INCEDI[EDI]  [EDI] +1 DECECX[ECX]  [ECX] -1 JGLBranch if [ECX]>0 MOVSUM, EAXM(SUM)  [EAX]

30 TU-Delft TI1400/12-PDS 30 Summation example Assembler code, Version 1 [4/4] LEAEBX, NUM1[EBX]  #NUM1 MOVECX, N[EXC]  M(N) MOVEAX, 0[EAX]  #0 MOVEDI, 0[EDI]  #0 L:ADDEAX, [EBX+EDI*4]Add next number to EAX INCEDI[EDI]  [EDI] +1 DECECX[ECX]  [ECX] -1 JGLBranch if [ECX]>0 MOVSUM, EAXM(SUM)  [EAX]

31 TU-Delft TI1400/12-PDS 31 Summation example Assembler code, Version 1 LEAEBX, NUM1[EBX]  #NUM1 MOVECX, N[EXC]  M(N) MOVEAX, 0[EAX]  #0 MOVEDI, 0[EDI]  #0 L:ADDEAX, [EBX+EDI*4]Add next number to EAX INCEDI[EDI]  [EDI] +1 DECECX[ECX]  [ECX] -1 JGLBranch if [ECX]>0 MOVSUM, EAXM(SUM)  [EAX]

32 TU-Delft TI1400/12-PDS 32 Summation example Assembler code, Version 2 LEAEBX, NUM1[EBX]  #NUM1 SUBEBX, 4 MOVECX, N[EXC]  M(N) MOVEAX, 0[EAX]  #0 L:ADDEAX, [EBX+ECX*4]Add next number to EAX LOOPL[ECX]  [ECX] -1 Branch if [ECX]>0 MOVSUM, EAXM(SUM)  [EAX] Q Why SUB EBX,4?

33 TU-Delft TI1400/12-PDS 33 Summation example Performance, Version 1 vs Version 2 LEAEBX, NUM1 SUBEBX, 4 MOVECX, N MOVEAX, 0 L:ADDEAX, [EBX+ECX*4] LOOPL MOVSUM, EAX LEAEBX, NUM1 MOVECX, N MOVEAX, 0 MOVEDI, 0 L:ADDEAX, [EBX+EDI*4] INCEDI DECECX JGL MOVSUM, EAX 1.Replaced 1xMOV with 1xSUB 2.Replaced 1xINC+1xDEC+1xJG with 1xLOOP Q What is the performance loss/gain?

34 TU-Delft TI1400/12-PDS 34 Summation example The.asm File.data NUM1DD0, 1, 2, -1, -2 NDD5 SUMDD0.code MAIN:LEAEBX, NUM1 SUBEBX, 4 MOVECX, N MOVEAX, 0 L:ADDEAX, [EBX+ECX*4] LOOPL MOVSUM, EAX CMPSUM,0 END MAIN

35 TU-Delft TI1400/12-PDS 35 Sorting example Java code int[] listarray = new list[n]; int temp; for(j=n-1, j>0, j--){ for(k=j-1, k>=0, k--){ if(list[j] > list[k]) { temp = list[k]; list[k] = list[j]; list[j] = temp; }

36 TU-Delft TI1400/12-PDS 36 Sorting Example Assembler code [1/4] LEAEAX, list[EAX]  #list MOVEDI, N[EDI]  n DECEDI [EDI]  n-1 init(j) outer:MOVECX, EDI[ECX]  j DECECX [ECX]  j-1 init (k) MOVDL, [EAX+EDI]load list(j) into DL inner:CMP[EAX+ECX], DLcompare list(k) to list(j) JLEnextif list(j) >= list(k) XCNG[EAX+ECX], DLswap list(j), list(k) MOV[EAX+ECX], DL new list(j) in DL next:DECECXdecrement k JGEinnerrepeat or terminate DECEDIdecrement j JGEouterrepeat or terminate

37 TU-Delft TI1400/12-PDS 37 Sorting Example Assembler code [2/4] LEAEAX, list[EAX]  #list MOVEDI, N[EDI]  n DECEDI [EDI]  n-1 init(j) outer:MOVECX, EDI[ECX]  j DECECX [ECX]  j-1 init (k) MOVDL, [EAX+EDI]load list(j) into DL inner:CMP[EAX+ECX], DLcompare list(k) to list(j) JLEnextif list(j) >= list(k) XCNG[EAX+ECX], DLswap list(j), list(k) MOV[EAX+ECX], DL new list(j) in DL next:DECECXdecrement k JGEinnerrepeat or terminate DECEDIdecrement j JGEouterrepeat or terminate

38 TU-Delft TI1400/12-PDS 38 Sorting Example Assembler code [3/4] LEAEAX, list[EAX]  #list MOVEDI, N[EDI]  n DECEDI [EDI]  n-1 init(j) outer:MOVECX, EDI[ECX]  j DECECX [ECX]  j-1 init (k) MOVDL, [EAX+EDI]load list(j) into DL inner:CMP[EAX+ECX], DLcompare list(k) to list(j) JLEnextif list(j) >= list(k) XCNG[EAX+ECX], DLswap list(j), list(k) MOV[EAX+ECX], DL new list(j) in DL next:DECECXdecrement k JGEinnerrepeat or terminate DECEDIdecrement j JGEouterrepeat or terminate

39 TU-Delft TI1400/12-PDS 39 Sorting Example Assembler code [4/4] LEAEAX, list[EAX]  #list MOVEDI, N[EDI]  n DECEDI [EDI]  n-1 init(j) outer:MOVECX, EDI[ECX]  j DECECX [ECX]  j-1 init (k) MOVDL, [EAX+EDI]load list(j) into DL inner:CMP[EAX+ECX], DLcompare list(k) to list(j) JLEnextif list(j) >= list(k) XCNG[EAX+ECX], DLswap list(j), list(k) MOV[EAX+ECX], DL new list(j) in DL next:DECECXdecrement k JGEinnerrepeat or terminate DECEDIdecrement j JGEouterrepeat or terminate

40 TU-Delft TI1400/12-PDS 40 Sorting Example Assembler code [4/4] LEAEAX, list[EAX]  #list MOVEDI, N[EDI]  n DECEDI [EDI]  n-1 init(j) outer:MOVECX, EDI[ECX]  j DECECX [ECX]  j-1 init (k) MOVDL, [EAX+EDI]load list(j) into DL inner:CMP[EAX+ECX], DLcompare list(k) to list(j) JLEnextif list(j) >= list(k) XCNG[EAX+ECX], DLswap list(j), list(k) MOV[EAX+ECX], DL new list(j) in DL next:DECECXdecrement k JGEinnerrepeat or terminate DECEDIdecrement j JGEouterrepeat or terminate Q Is this code a correct implementation of the Java code? int[] listarray = new list[n]; int temp; for(j=n-1, j>0, j--){ for(k=j-1, k>=0, k--){ if(list[j] > list[k]) { temp = list[k]; list[k] = list[j]; list[j] = temp; }

41 TU-Delft TI1400/12-PDS 41 IA-32 1.Introduction 2.Registers 3.Memory Layout 4.Instructions 5.Examples of Assembler Code for IA-32 6.Subroutines  really long

42 TU-Delft TI1400/12-PDS 42 Subroutines CALL sub Return address is saved on stack (ESP register) Return is RET [EIP]  #sub [EIP]  [ESP] [ESP]  [ESP]+4

43 TU-Delft TI1400/12-PDS 43 Stack instructions ESP register is used as stack pointer PUSH src [ESP]  [ESP] - #4 M([ESP])  [src] POP dst [dst]  M([ESP]) [ESP]  [ESP] + #4 PUSHAD (POPAD) push (pop) all 8 registers on (from) stack

44 TU-Delft TI1400/12-PDS 44 Stack frames [1/4].... PUSH NParameter n on stack 2000CALLSub1Call subroutine at 2400........... 2004 N 10056 2400 ESP EIP 10052 Note: Sub1 starts at address 2400 Stack Pointer Stack program counter stack pointer

45 TU-Delft TI1400/12-PDS 45 Stack frames [2/4].... PUSH NParameter N on stack 2000CALLSub1Call subroutine at 2400........... N 10052 2000 ESP EIP 10052 Note: Sub1 starts at address 2400 Stack Pointer Stack program counter stack pointer

46 TU-Delft TI1400/12-PDS 46 Stack frames [3/4].... PUSH NParameter n on stack 2000CALLSub1Call subroutine at 2400........... 2004 N 10048 2000 ESP EIP 10052 Note: Sub1 starts at address 2400 Stack Pointer Stack program counter stack pointer 10048

47 TU-Delft TI1400/12-PDS 47 Stack frames [4/4].... PUSH NParameter n on stack 2000CALLSub1Call subroutine at 2400........... 2004 N 10048 2400 ESP EIP 10052 Note: Sub1 starts at address 2400 Stack Pointer Stack program counter stack pointer 10048

48 TU-Delft TI1400/12-PDS 48 Subroutine Sub1 Sub1:PUSHEAXSave EAX PUSHEBXSave EBX MOVEAX, [EDI + 12]n to EAX DECEAX.... PUSHEAXLoad n-1 on stack L:CALLSub2Call subroutine POPNPut result in M(N) POPEBXRestore EBX POPEAXRestore EAX RETreturn

49 TU-Delft TI1400/12-PDS 49 Stack frame in Sub1 [EBX] [EAX] Return Address N 10040 ? ESP EIP 10052 Stack frame at arrow 10036 2400:PUSHEAX PUSHEBX MOVEAX, [EDI + 12] DECEAX Q What is the value op EIP? After PUSH EBX 10040

50 TU-Delft TI1400/12-PDS 50 Subroutine Sub1 2400PUSHEAXSave EAX PUSHEBXSave EBX MOVEAX, [EDI + 12]n to EAX DECEAX.... PUSHEAXLoad n-1 on stack L:CALLSub2Call subroutine POPNPut result in M(N) POPEBXRestore EBX POPEAXRestore EAX RETreturn After DEC EAX

51 TU-Delft TI1400/12-PDS 51 Stack frame in Sub1 Stack frame at arrow [EBX] [EAX] Return Address N 10040 ? EIP 10052 10040 n-1 EAX ESP 2400:PUSHEAX PUSHEBX MOVEAX, [EDI + 12] DECEAX After DEC EAX

52 TU-Delft TI1400/12-PDS 52 Subroutine Sub1 2400:PUSHEAXSave EAX PUSHEBXSave EBX MOVEAX, [EDI + 12]n to EAX DECEAX.... PUSHEAXLoad n-1 on stack L:CALLSub2Call subroutine POPNPut result in M(N) POPEBXRestore EBX POPEAXRestore EAX RETreturn After PUSH EAX

53 TU-Delft TI1400/12-PDS 53 Stack frame in Sub1 Stack frame at arrow N-1 [EBX] [EAX] Return Address N 10036 ? EIP 10052 10036 N-1 EAX ESP 2400:PUSHEAX PUSHEBX MOVEAX, [EDI + 12] DECEAX.... PUSHEAX After PUSH EAX 10040

54 TU-Delft TI1400/12-PDS 54 Stack frame in Sub1 Stack frame at arrow Return Address [EBX] [EAX] Return Address N 10032 ? EIP 10052 10036 N-1 EAX ESP 2400:PUSHEAX.... PUSHEAX L:CALLSub2 After CALL SUB2 N-1 10032 10040

55 TU-Delft TI1400/12-PDS 55 Stack frame in Sub2 Stack frame at arrow Return Address N-1 [EBX] [EAX] Return Address n 10032 ? EIP 10052 10036 N-2 EAX ESP Sub2:MOVEAX, [EDI+4] DECEAX MOV[EDI+4], EAX RET After DEC EAX 10040

56 TU-Delft TI1400/12-PDS 56 Stack frame in Sub2 Stack frame at arrow Return Address N-1 [EBX] [EAX] Return Address n 10032 ? EIP 10052 10040 N-2 EAX ESP Sub2:MOVEAX, [EDI+4] DECEAX MOV[EDI+4], EAX RET After MOV…


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