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A NALOG TO D IGITAL C ONVERTERS Stu Godlasky Nikita Pak James Potter

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I NTRODUCTION What is an analog to digital converter (ADC) Going from analog to digital Types and properties of ADC

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W HAT IS AN A NALOG TO D IGITAL C ONVERTER Converts an analog signal to discrete time digital Computers need digital. (On / Off, High / Low, 1/0)

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G OING FROM A NALOG TO D IGITAL Two step process 1) Sampling – Measuring analog signal at uniform time intervals 2) Quantization – Assigning discrete measurements a binary code (each sample will have a binary number associated with it) T 1 T 2 T 3 T 4 Example of digital signal from 3 bit ADC

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A LIASING Every analog signal has a frequency Nyquist Frequency (half sampling frequency) Aliasing occurs when signal above Nyquist frequency

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Q UANTIZATION E RROR Analog (infinite values) – Digital (finite values) Upon reconstruction of analog signal Increases as resolution decreases Resolution - Q E FSR - full scale voltage range N = Number of discrete voltage intervals N = 2 k where k is the number of bits

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Q UANTIZATION E RROR Quantized signal only has values at midpoint of voltage band

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T YPES OF A NALOG TO D IGITAL C ONVERTERS Dual Slope A/D Converter Successive Approximation A/D Converter Flash A/D Converter Delta – Sigma A/D Converter

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D UAL S LOPE A NALOG TO D IGITAL C ONVERTER Also referred to as an Integrating ADC Integrator

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D UAL S LOPE A NALOG TO D IGITAL C ONVERTER Converts in two phases (ramp up / ramp down ) Input voltage measurement not dependant on integrator components

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D UAL S LOPE A NALOG TO D IGITAL C ONVERTER Pros Conversion result is insensitive to errors in the component values Fewer adverse affects from noise High accuracy Cons o Slow o Accuracy is dependant on the use of precision external components o Cost

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S UCCESSIVE A PPROXIMATION A NALOG T O D IGITAL C ONVERTER DAC = Digital to Analog Converter EOC = End of Conversion SAR = Successive Approximation Register S/H = Sample and Hold Circuit V in = Input Voltage V ref = Reference Voltage

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S UCCESSIVE A PPROXIMATION A NALOG TO D IGITAL C ONVERTER Uses an n-bit DAC and original analog results Performs a bit by bit comparison of V DAC and V in If V in > V REF / 2 MSB set to 1 otherwise 0 If V in > V DAC Successive Bits set to 1 otherwise 0

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S UCCESSIVE A PPROXIMATION ADC E XAMPLE 10 bit ADC V in = 0.6 V V ref = 1V N = 2 n (n = number of bits) N = 2 10 = 1024 V ref = 1V/ 1024 = V (resolution)

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S UCCESSIVE A PPROXIMATION D IGITAL TO A NALOG C ONVERTER Pros Capable of high speed and reliable Medium accuracy compared to other ADC types Good tradeoff between speed and cost Capable of outputting the binary number in serial (one bit at a time) format. Cons o Higher resolution successive approximation ADCs will be slower

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F LASH A NALOG TO D IGITAL C ONVERTER Also called a parallel ADC 2 N – 1 Comparators 2 N Resistors Control Logic (encoder)

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F LASH A NALOG TO D IGITAL C ONVERTER Uses the resistors to divide reference voltage into intervals Uses comparators to compare V in and the reference voltages Encoder takes the output of comparators and uses control logic to generate binary digital output

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F LASH A NALOG TO D IGITAL C ONVERTER Pros Very Fast (Fastest) Very simple operational theory Speed is only limited by gate and comparator propagation delay Cons o Expensive o Prone to produce glitches in the output o Each additional bit of resolution requires twice the comparators and resistors

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S IGMA -D ELTA A NALOG TO D IGITAL C ONVERTER Input over sampled, goes to integrator Integration compared with ground Iteration drives integration of error to zero Output is a stream of serial bits

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S IGMA -D ELTA A NALOG TO D IGITAL C ONVERTER Pros High resolution No need for precision components Cons o Slow due to over sampling o Only good for low bandwidth

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C OMPARISON OF ADC S TypeSpeed (relative) Cost (relative) Resolution Dual SlopeSlowMed12-16 FlashVery FastHigh4-12 Successive Approx Medium – Fast Low8-16 Sigma – Delta SlowLow12-24

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A NALOG TO D IGITAL C ONVERTER A PPLICATIONS Nikita Pak

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A NALOG TO D IGITAL C ONVERTER A PPLICATIONS Music recording Data acquisition/measurement devices thermocouples digital multimeters strain gauges Consumer Products cell phones digital cameras

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M USIC R ECORDING A to D used to convert sound pressure waves into discrete digital signal (later, D to A used to convert back to an electrical signal for a speaker) Saves a tremendous amount of space Ex. CD samples at 44.1 kHz (Nyquist frequency = kHz is higher than human ear can detect) CD recording often done with flash A to D

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D ATA A CQUISITION Data acquisition: the process of obtaining signals from sensors that measure physical conditions Sensors give analog voltage that must be converted to work on a computer Most National Instruments DAQ’s use successive approximation A to D

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M EASUREMENT D EVICES Thermocouple: a junction of dissimilar metals creates a voltage difference that is temperature dependent Digital multimeter: converts signal to a voltage and amplifies it for measurement More accurate than analog counterparts

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M EASUREMENT D EVICES Strain gauge: most common type measures the change in resistance as a metal pattern is deformed

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C ONSUMER P RODUCTS Cell phones: convert your voice into a digital signal so it can be more efficiently transmitted by compressing the signal Digital camera ccd: absorbed photons create charges that are converted into a sequence of voltages These voltages are converted to a digital signal Both often use flash A to D

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ADC ON Y OUR M ICROCONTROLLER Input Pins ADC Built-into MC9S12C32

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ADC IN B LOCK D IAGRAM ATD 10B8C Port AD

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D ETAILS OF ATD 10B8C Analog-To-Digital Resolution: 8 or 10 Bits (manually chosen) 8-Channel multiplexed inputs Conversion time: 7 µs (for 10 bit mode) Optional external trigger “Successive approximation” type ADC

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ATD 10B8C B LOCK D IAGRAM

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Reference Voltages Source V source Results of Successive Approximation “Holds” Source Voltage

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R EGISTERS AND S ETTING U P Y OUR ATD10B8C James Potter

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ADC R EGISTERS All information about registers found in Chapter 8 of MC9S12C Family Reference Manual 8 Result Registers 6 Control Registers 2 Status Registers 2 Test Registers 1 Digital Input Enable Register 1 Digital Port Data Register

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R ESULT R EGISTERS

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8 registers, Each with High and low byte

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R ESULT R EGISTERS : L EFT -J USTIFIED (D EFAULT ) High Byte Low Byte

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R ESULT R EGISTERS : R IGHT -J USTIFIED High Byte Low Byte

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C ONTROL R EGISTERS

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C ONTROL R EGISTERS : ATDCTL2

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C ONTROL R EGISTERS : ATDCTL3

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C ONTROL R EGISTERS : ATDCTL4

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C ONTROL R EGISTERS : ATDCTL5

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S INGLE C HANNEL (MULT = 0) S INGLE C ONVERSION (SCAN = 0) Port AD ATD Converter Result Register Interface ATDDR 0 ATDDR1 ATDDR2 ATDDR3 ATDDR4 ATDDR5 ATDDR6 ATDDR7

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S INGLE C HANNEL (MULT = 0) C ONTINUOUS C ONVERSION (SCAN = 1) Port AD ATD Converter Result Register Interface ATDDR 0 ATDDR1 ATDDR2 ATDDR3 ATDDR4 ATDDR5 ATDDR6 ATDDR7

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M ULTIPLE C HANNEL (MULT = 1) S INGLE C ONVERSION (SCAN = 0) Port AD ATD Converter Result Register Interface ATDDR 0 ATDDR1 ATDDR2 ATDDR3 ATDDR4 ATDDR5 ATDDR6 ATDDR7

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S INGLE C HANNEL (MULT = 1) C ONTINUOUS C ONVERSION (SCAN = 1) Port AD ATD Converter Result Register Interface ATDDR 0 ATDDR1 ATDDR2 ATDDR3 ATDDR4 ATDDR5 ATDDR6 ATDDR7

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S TATUS R EGISTERS

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S TATUS R EGISTER 0: ATDSTAT0

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S TATUS R EGISTER 1: ATDSTAT1

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S ETTING U P Y OUR ATD10B8C

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S ETTING U P THE ATD Step 1: Power-up the ATD and define settings in ATDCTL2 ADPU = 1 powers up the ATD ASCIE = 1 enables interrupt Step 2: Wait for ATD recovery time (~ 20μs) before proceeding Step 3: Set number of successive conversions in ATDCTL3 S1C, S2C, S4C, S8C determine number of conversions (see Table 8-4)

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S ETTING U P THE ATD Step 4: Configure resolution, sampling time, and ATD clock speed in ATDCTL4 PRS0, PRS1, PRS2, PRS3, PRS4 set sampling rate (see Table 8-6) SRES8 sets resolution to 8-bit (= 1) or 10-bit (= 0) Step 5: Configure starting channel, single/multiple channel, SCAN and result data signed or unsigned in ATDCTL5 CC, CB, CA determine input channel (see Table 8-12) MULT sets single (= 0) or multiple (= 1) inputs SCAN sets single (= 0) or continuous (= 1) sampling DJM sets output format as left-justified (=0) or right-justified (=1) DSGN sets output data as unsigned (=0) or signed (=1)

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T HANK Y OU

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