Presentation on theme: "CS 423 – Operating Systems Design Lecture 9 –Context Switches, Coordination Roy Campbell Fall 2010."— Presentation transcript:
CS 423 – Operating Systems Design Lecture 9 –Context Switches, Coordination Roy Campbell Fall 2010
Context Switch PCBs move from queue to queue as they change state – Red circles indicate where context switches can occur
Context Switch Switch between one program control flow and another Context – Machine level: – integer/floating pt/stack/heap/PCB registers – status registers: overflow, branch – memory status: tlb, L1, L2, L3, cache, virtual memory status, addressing faults, memory ops – pipeline/hyperthread status – interrupts: status, pending
Instruction Seq for switch Hardware: – IA86 – heavy weight CALL, TSS context switch instructions change registers and stacks. Software: – Light weight, do it yourself register changes. – must change context prior to restore
Instruction Seq for switch Hybrid: – Hardware: change program counter/registers via interrupt or operation basic primitive – software must add any additional changed context after switch. – Restoring program counter using hardware primitive – must change context prior to restore
Additional Context Switch Overhead Application State – stack, heap, sockets… Virtual Machine State – i/o and network support and VM mappings Virtual Memory State - vmtable, tlb cache, User Process, Thread State – thread/process stack, heap, ready queue, exception handling Kernel Process, Thread State – kernel thread/process stack, heap, interrupt vectors
Optimizing Context Switch Lazy context switching – wait until dispatch knows what is running next and then change minimized context. When switching between different protection domains, check parameters. Minimize protection checking – Light Remote Procedure Call – don’t check parameters if remain in same protection domain
Switch Details How many registers need to be saved/restored? – MIPS 4k: 32 Int(32b), 32 Float(32b) – Pentium: 14 Int(32b), 8 Float(80b), 8 SSE(128b),… – Sparc(v7): 8 Regs(32b), 16 Int regs (32b) * 8 windows = 136 (32b)+32 Float (32b) – Itanium: 128 Int (64b), 128 Float (82b), 19 Other(64b) retpc is where a return should jump to. – In reality, this is implemented as a jump Software switch is often implemented as assembly!
Intel Task Switching Instructions JMP, Call to a Task Segment S in a GDT (Global Descriptor Table) JMP, Call to a task-gate descriptor (contains a TSS) in the GDT, or current LDT Implicit call to an interrupt-handler task Implicit call to an exception-handler task A return (IRET) when the NT flag (Nested Task) is set. Used to return from interrupts.
Intel CALL Instruction This instruction can be used to execute four types of calls: Near Call — A call to a procedure in the current code segment (the segment currently pointed to by the CS register), sometimes referred to as an intrasegment call. Far Call — A call to a procedure located in a different segment than the current code segment, sometimes referred to as an inter-segment call. Inter-privilege-level far call — A far call to a procedure in a segment at a different privilege level than that of the currently executing program or procedure. Task switch — A call to a procedure located in a different task. See Chapter 7, “Task Management,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for information on performing task switches with the CALL
Where to look for more info The key function for context switching is __switch_to() in ocess_32.c.http://lxr.linux.no/linux+v2.6.35/arch/x86/kernel/pr ocess_32.c The difficulties of optimizing context switching on i7: posts.php Intel processor manuals can be found here: See Page 120 for CALL instruction
Where to look for more info The key function for context switching is __switch_to() in x86/kernel/process_32.c.http://lxr.linux.no/linux+v2.6.35/arch/ x86/kernel/process_32.c Reason given for software switching – difficult to recover from errors using hardware switch (particularly segment issues.)
Cost of Context Switch 2.8 GHZ Pentium P4, approx 811 ns HW for interrupt, 184 ms address space switch, 67 ns to store/restore registers. As CPUs got faster, switches got faster but took relatively more time as clocks got faster. BUT, software switching vs hardware switching is used because can recover from errors. NOTE: context switching involves invalidating caches - cost varies and can be very large.
Arm Context switching “Context Switch Overheads for Linux on ARM Platforms” Francis M. David Jeffrey C. Carlyle Roy H. Campbell
Coordination Mutual Exclusion Signals – Buffering – Gang scheduling – Simultaneity – multiple processes waiting for two or more shared events Priorities State machine and other solutions – Atomicity and computation