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Slide 1Michael Flynn EE382 Winter/99 EE382 Processor Design Stanford University Winter Quarter 1998-1999 Instructor: Michael Flynn Teaching Assistant:

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Presentation on theme: "Slide 1Michael Flynn EE382 Winter/99 EE382 Processor Design Stanford University Winter Quarter 1998-1999 Instructor: Michael Flynn Teaching Assistant:"— Presentation transcript:

1 Slide 1Michael Flynn EE382 Winter/99 EE382 Processor Design Stanford University Winter Quarter 1998-1999 Instructor: Michael Flynn Teaching Assistant: Steve Chou Administrative Assistant: Susan Gere Lecture 1 - Introduction

2 Slide 2Michael Flynn EE382 Winter/99 Class Objectives l Learn theoretical analysis and limits —develop intuition —project long-term trends and bound design space more efficiently than simulation l Learn models for VLSI component cost tradeoffs —emphasis on microprocessor l Learn modeling techniques for computer system performance —emphasis on queuing l Put it all together to balance system performance and cost —Emphasis on multiprocessors, memory, and I/O —Practical examples and design targets

3 Slide 3Michael Flynn EE382 Winter/99 Course Prerequisites l Computer Architecture and Organization (EE282) —Instruction Set Architecture —Machine Organization —Basic Pipeline Design —Cache Organization —Branch Prediction —Superscalar Execution In-Order Out-of-Order l Statistics —Basic probability distribution functions statistical measures —Familiarity with stochastic processes and Markov models is helpful, but not required

4 Slide 4Michael Flynn EE382 Winter/99 Course Information l Access to the course web page is necessary —Course info, assignments, old exams, design tools,FAQs,... l Textbook and reference material —Computer Architecture: Pipelined and Parallel Processor Design, Michael J. Flynn l Problem set and design problem philosophy —Learn by doing: maximize learning/effort l Exam philosophy —Extend what you have learned —Open-book, not a speed or trick contest l You are expected to give us feedback —Questions, office hours, email, surveys

5 Slide 5Michael Flynn EE382 Winter/99 Grading l Problem Sets and Design Problems 40% —6 problem sets, —2 design problems l Midterm 20% l Final Exam 40% —Covers entire course —Scheduled March 15, 8:30-11:30AM

6 Slide 6Michael Flynn EE382 Winter/99 Key Concepts of Abstraction l Instruction Set Architecture (ISA) —Functional interface for assembly-language programmer —Examples: SGI MIPS, Sun SPARC, PowerPC, HPPA, DEC Alpha, Intel (x86), IBM System/390, IBM AS/400 l Implementation (Machine Organization) —Partitioning into units and logic design —Examples Intel386 CPU, Intel486 CPU, Pentium ® Processor, Pentium ® Pro Processor Alpha 21064, 21164, 21264 l Realization —Physical fabrication and assembly —Examples IBM 709(‘54) built with vacuum tubes and 7090(‘59) built with transistors Pentium Processor in 0.8  m, 0.6  m, 0.35  m BiCMOS/CMOS

7 Slide 7Michael Flynn EE382 Winter/99 Instruction Set Architecture l “... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flow and controls, the logical design, and the physical implementation.” Amdahl, Blaauw, and Brooks, 1964 l Consists of: —Organization of storage —Data types —Encodings and representations (instruction formats) —Instruction (or Operation Code) Set —Modes for addressing data Items and instructions —Program visible exceptional conditions l Specifies requirements for binary compatibility across implementations

8 Slide 8Michael Flynn EE382 Winter/99 Instruction Set Types l Load/Store (L/S) —Only load and store instructions refer to memory no memory ALU ops —used by several microprocessors Power PC, HP, DEC Alpha l Register/Memory (R/M) —ALU operations can have either source or destination in memory —Used by mainframes and most microprocessors IBM System/370, Intel Architecture (x86), all x86 compatables l Register or Memory (R+M) —ALU operations can have any/all operands in memory —Not used commonly now DEC Vax

9 Slide 9Michael Flynn EE382 Winter/99 L/S ISA General Characteristics l 32 GPR x 32b....more recently 64b l instr size: 32b... more recently 64b l instr types —R 1 <- R 2 op R 3 for ALU ops —R 1 MEM [R B,D] for LD/ST

10 Slide 10Michael Flynn EE382 Winter/99 R/M ISA General Characteristics l 16 GPR x 32b l instr size...16b, 32b, 48b l instr types —RR R 1 <- R 1 op R 2 —RM R 1 <- R 1 op MEM [R B,R X,D] —MM MEM 1 [R B,R X,D] <- MEM 1 [R B,R X,D] op MEM 2 [R B,R X,D] used for character, decimal ops only.

11 Slide 11Michael Flynn EE382 Winter/99 ISA Syntax Terminology l OP.type destination, source1,source2 —eg ADD.F R1,R2,R3 puts result of floating pt. add in floating reg 1. —OP without type implies integer type unless fp is clear from the context. —destination is always first operand, so that store is ST MEM [R B,R X,D], R2

12 Slide 12Michael Flynn EE382 Winter/99 ISA Assumptions l assume all i.s. have a PSW and condition codes...CC l Branch is BC.CC target, target is either R or Mem. l unconditional branch is BR, even though it’s implemented with BC l other branches BCT, BAL (branch and link)

13 Slide 13Michael Flynn EE382 Winter/99 Moore’s Law Moore’s Law: No. Tx per chip increases 4X every 3 years CAGR = 60% Source: Intel Transistors Per Die Pentium™ Processor 8080 8086 80286 Intel386™ Processor Intel486™ Processor 200019701975198019851990 1995 4004 10 8 10 7 10 6 10 5 10 4 10 3 10 2 10 1 1 16M 1K 4K 16K 64K 256K 1M 4M

14 Slide 14Michael Flynn EE382 Winter/99 Die Size Growth Source: Intel

15 Slide 15Michael Flynn EE382 Winter/99 Finer Lithography Source: Intel

16 Slide 16Michael Flynn EE382 Winter/99 Limits on scaling l As device sizes get smaller there are difficulties maintaining the rate of down sizing of feature sizes l It currently appears that around 50nm several factors may limit scaling —hot carrier effects —time dependent dielectric breakdown —gate tunneling current —short channel effects and effect on V T

17 Slide 17Michael Flynn EE382 Winter/99 Beyond CMOS MOSFETs l If “limits” prove real; there are alternative technologies with system’s implications —low temperature CMOS —sub threshold logic —new gate oxide materials —SOI

18 Slide 18Michael Flynn EE382 Winter/99 Fabrication Facility Costs Dollars in Millions Source: VLSI Research, Inc. Moore’s Second Law: Fab Costs Grow 40% Per Year

19 Slide 19Michael Flynn EE382 Winter/99 Microprocessor Business Model l New “generation” of silicon technology every 2.5-3 years —30% reduction in linear dimensions => 50% in area —30% reduction in device delay => 50% increase in speed —Used to reduce cost and improve performance on previous generation microprocessor —Used to enable new generation of microprocessor with wider, more parallel, more functional machine organization —Incremental changes between generations l Business growth enables investment in new technology —Driven by performance, new applications, and “dancing bunny people”

20 Slide 20Michael Flynn EE382 Winter/99 Performance Growth Workstation Performance Improving 54% per year That’s almost 1% per week! Figure 1.20 from P&H

21 Slide 21Michael Flynn EE382 Winter/99 PC Shipment Growth Performance Growth and New Applications Drive Volume Source: Dataquest by A. Yu in IEEE Micro 12/96

22 Slide 22Michael Flynn EE382 Winter/99 System Price/Performance DEC VAX11/780 1 MIPS 1 MB $200K $200K per MIPS 1977 IBM System 360/50 0.15 MIPS 64 KB $1M $6.6M per MIPS Dell Dimension XPS-300 725 MIPS 64 MB $2412 (1/4/98) $3.33 per MIPS 1965 1998 Photographs from Virtual Computing History Group

23 Slide 23Michael Flynn EE382 Winter/99 Representative System L2 Cache Pipelines Registers L1 Icache L1 Dcache CPU Chipset Memory I/O Bus(es)

24 Slide 24Michael Flynn EE382 Winter/99 Summary l Current architectures exploit parallelism for performance —Multiple pipelines and caches —Multiprocessors l Technology costs are increasing rapidly —High volume is critical to recover costs interface standards and evolution necessary —Product success depends on cost-effective area allocation and partitioning l Technology capacity and performance increasing rapidly —Critical to evaluate broad space of design options at each generation Opportunity to learn from the past and to innovate Theoretical analysis and modeling combined with design targets are powerful tools for developing computer systems. This course will help prepare you to apply those for your future career in theory or practice.

25 Slide 25Michael Flynn EE382 Winter/99 This Week l Check access to the web page —Make sure you can read and print —First problem set will be posted by Friday l Reading —Scan Chapter 1 —Sections 2.1,2.2 l Room Change —move to Gates B03 —no festival Friday lecture

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