9 The Entire Packaging History Hot for the 21st CenturyFC-BGAFlip Chip(C4)Flip Chip(re-Engineered)BGAChip-on-BoardLead FrameTBGASMTTCP (TAB)SpiderFeed-thrumBGACSP/FC-BGAFlip Chip StripSMTmicro-SMTBeam Lead Chip
10 Packaging Trends Perimeter Leads Area Array Size: chip scale Packaging: minimalPackaging: post- and concurrentPaths/lead length: shorterSMT3COB & TAB2DCAIC1ULTIMATE
11 Is Flip Chip a True PACKAGE? What is a PACKAGE?Is Flip Chip aTrue PACKAGE?
12 PACKAGE the Translation: IC to PCB Environmental Protection RemovabilityEnvironmentalProtectionStandardization
16 Bumping Methods Attach discrete spheres; Au, Cu, Sn/Pb Print joining mat's; Sn/Pb or Conductive AdhesiveVacuum deposit metal: old, still aliveElectrolytic plating; Au, Cu, Sn/Pb, Ni (cost issue?)Electroless plating; Au, Cu, Ni (NEWER)Fluid jet molten metal; Sn/Pb (VERY NEW)Stud bump with; Sn/Pb, CU or Au (single chip)Material transfer; Sn/Pb or Cond. Adhes.; paste or filmmetal vapor
17 The 2nd Generation FC Problem Switch to organic substrateCauses large thermal mismatchLow reliability in thermocycleMismatch must be addressedlow CTE organic substratecolumns instead of bumpsnon-fatiguing joints???mechanical coupling: chip-to-substrate
18 Thermal Mismatch Kills Reliability H e a t i n gC o o l i n gCHIPSn/Pb
28 Pre-Dispense Solid on Substrate Film-on-PCBSpecial, expensive equipmentNot an SMT processDoesn’t address underfill problemsAn old concept?
29 Anisotropic Conductive Adhesive ACA film has a built-in underfill and is the 1st example of pre-dispensed solid underfill.
30 Pre-Dispense Solid on Chip Wafer-level appliedSelf-fluxingDry solidIntegral to Flip ChipTrue SMT processTransparent to assemblerCan be reworkable
31 Integrated Flux-Underfill Liquid polymer-based composition is coated onto Flip Chips at wafer-level and then converted to a SOLID that: (1) Permits a bumped wafer to be diced into Flip Chips. (2) Provides flux for assembly. (3) Liquefies to a thermoplastic underfill during reflow. (4) Polymerizes and wets substrate during reflow step . (5) Remains reworkable after reflow stage cure.
32 Ramifications: FC becomes a std. SMT process. FC becomes CSP if reworkable.Underfill becomes a semiconductor process.The ready-to-bond FC becomes the most cost-effective minimal package.Success can make this package the dominant micropackage.
33 Assembly Process Pick & Place FC from any format Reflow Test flux melts/activatesunderfill liquefies/wetssolder melts/forms jointunderfill solidifiesTestRework if required
34 TIME in Solder Reflow Oven Assembly ProcessSolder joints form, underfill properties generatedTEMPMelts; flux activates, begins to bond to substrateFlux has deactivated, material is now an underfillTIME in Solder Reflow Oven
35 Issues & Challenges Materials; single or multiple? Shelf life, what is required?What wafer Coating process?Dicing with polymer in place?Assemblyvoiding, filleting, adhesionprocess sensitivity
36 INTEGRTATED/FLUXFILL FLIP CHIPINTEGRTATED/FLUXFILLType 1 - Single material converts from flux to underfill during reflowSolid FluxFLIP CHIP
37 INTEGTRATED FLUX/UNDERFILL FLIP CHIPINTEGTRATED FLUX/UNDERFILLType 2 - Two separate materialsSolid FluxSolid ThermoplasticUnderfillFLIP CHIPMany variations
38 Status Technology 2-LAYER 1-LAYER MATERIALS complete being optimized WAFER COATINGbeing optimizedselection stageDICINGFeasibilityconfirmedto bedeterminedFC ASSEMBLYconfirmedto bedeterminedRELIABILITYto bedeterminedto bedetermined
39 Phase 1 Test PlatformTransparent 12 mm x 12 mm Flip Chip Bonded to Copper with single-layer Flux/Underfill by running through an IR reflow oven at 220oCCopper sheetPurchased quartz FC with Sn/Pb bumpsFlux/underfill after heatingDelco is not a sponsor or participant
40 Conclusions Today’s underfills impede FC FC = SMT: required for max. successUnderfill can be a semicon processFC will become a CSP againResult: best micropackage solution
41 The Ultimate Micro Package Everything should be made as simple as possible but not simpler.Albert EinsteinJust add heat; some assembly required.