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April 30, 2014 1 A New Tool for Designer-Level Verification: From Concept to Reality April 30, 2014 Ziv Nevo IBM Haifa Research Lab.

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Presentation on theme: "April 30, 2014 1 A New Tool for Designer-Level Verification: From Concept to Reality April 30, 2014 Ziv Nevo IBM Haifa Research Lab."— Presentation transcript:

1 April 30, A New Tool for Designer-Level Verification: From Concept to Reality April 30, 2014 Ziv Nevo IBM Haifa Research Lab

2 April 30, Overview Designer-level verification (DLV) DLV tools: historical perspective at IBM Our latest recipe

3 April 30, Designer-level verification (DLV)

4 April 30, Life without DLV Logic designer Verification engineer spec RTL

5 April 30, Weeks later… Logic designer Verification engineer spec fail trace

6 April 30, DLV ≈ “ Developer testing ” (standard practice in SW) Verification engineer Logic designer RTL Basic checks

7 April 30, What activities does DLV include? Observing mainstream behavior Exploring corner cases Checking assertions and coverage points Bug hunting Debugging Observation Lightweight verification

8 April 30, Verification: tools of the trade Simulator Testbench HVL Methodology Scripts Formal Assertions Coverage … Logic designer Verification engineer

9 April 30, DLV: what should the tools be? Logic designer Simulator Testbench HVL Methodology Scripts Formal Assertions Coverage …

10 April 30, DLV tools: historical perspective at IBM

11 April 30, Idea 1: TIMEDIAG (1997) Specify input value/function/random Loop cycle (count/random/condition)

12 April 30, Idea 1: TIMEDIAG (1997) GenRand  Random instantiation  Simulation  Checking

13 April 30, TIMEDIAG ingredients simulation Waveform- based interface complex interleavings What’s missing? Interactive define/run/view Event-guided test cases Formal analysis

14 April 30, What activities does DLV include? Observing mainstream behavior Exploring corner cases Checking assertions and coverage points Bug hunting Debugging Observation Lightweight verification

15 April 30, Idea 2: PathFinder (2002) Define events View trace Find a trace (formal analysis)

16 April 30, Idea 2: PathFinder (2002) Main flow: Specify events Find trace View trace Minor feature: Edit inputs on waveform Simulate

17 April 30, PathFinder ingredients waveform- based interface simulation Interactive define/run/view Event- guided test cases Formal analysis What’s missing? Simple driving (default is random) Fast simulation Integration with common tools

18 April 30, What activities does DLV include? Observing mainstream behavior Exploring corner cases Checking assertions and coverage points Bug hunting Debugging Observation Lightweight verification

19 April 30, Another DLV tool

20 April 30, Jasper Visualize

21 April 30, Our latest recipe

22 April 30, Latest recipe: Diver Main flow Specify inputs Simulate View trace IBM Debug and Verification Tool for Designers (DIVER) scenario editor Specify expected results View unexpected results

23 April 30, Latest recipe: Diver Additional variations Repetitions and delays Specify events on outputs Run-to-failure Simulate or run formal engine Assertions and coverage

24 April 30, Debugging Import trace Trace from simulation of integrated component Scenario for designer-level component

25 April 30, Diver ingredients simulation Waveform- based interface Interactive define/run/view Event- guided test cases Formal analysis Climate for DLV

26 April 30, What activities does DLV include? Observing mainstream behavior Exploring corner cases Checking assertions and coverage points Bug hunting Debugging Observation Lightweight verification

27 April 30, Conclusions DLV activity should scale linearly with the amount of effort spent Recommended recipe: – Waveform-based interface – Interactive define/run/view – Integration with common tools – Driving inputs – Simulation – Event-based test cases – A touch of formal analysis

28 April 30, Questions?


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