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09/16/2002 ICCD 2002 A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors* *supported in part.

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Presentation on theme: "09/16/2002 ICCD 2002 A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors* *supported in part."— Presentation transcript:

1 09/16/2002 ICCD 2002 A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors* *supported in part by DARPA through the PAC-C program and NSF Oguz Ergin, Kanad Ghose, Gurhan Kucuk, Dmitry Ponomarev Department of Computer Science State University of New York Binghamton, NY International Conference on Computer Design (ICCD 2002), September 16 th 2002

2 09/16/2002 ICCD 2002 A Superscalar Datapath IQ Function Units Instruction Issue F1D1 FU1 FU2 FUm ARF Result/status forwarding buses EX Instruction dispatch Architectural Register File F2 Fetch Decode/Dispatch D2 D-cache LSQ ROB

3 09/16/2002 ICCD 2002 Motivation Comparators are in a pervasive use in modern datapaths. They are used in: Issue queues Load-Store queues TLBs Caches Associatively-addressed Reorder Buffers Dependency checking logic CAM-based rename tables

4 09/16/2002 ICCD 2002 Motivation (continued) Traditional comparators dissipate energy on mismatches In many cases, mismatches are much more frequent than matches To save energy, we propose two dissipate-on- match comparators: A Two stage Domino-style design Pass-logic single stage design First, traditional comparator…

5 09/16/2002 ICCD 2002 Traditional 8-bit Pull-Down Comparator precharge Evaluation

6 09/16/2002 ICCD 2002 Two-Stage Domino-Style Comparator Precharge Discharge Propagation Evaluation (Conditional evaluation)

7 09/16/2002 ICCD 2002 Pass Logic, Single-Stage Comparator (PLSSC) Propagation Precharge Discharge Evaluation

8 09/16/2002 ICCD 2002 Timing Diagrams

9 09/16/2002 ICCD 2002 Experimental Setup (AccuPower, DATE’02) Compiled SPEC benchmarks Datapath specs Performance stats VLSI layout data SPICE deck SPICE Microarchitectural Simulator Energy/Power Estimator Power/energy stats SPICE measures of Energy per transition Transition counts, Context information

10 09/16/2002 ICCD 2002 Variation of Response Time with Vs

11 09/16/2002 ICCD 2002 Variation of Energy Dissipation with Vs

12 09/16/2002 ICCD 2002 Matching Statistics: the Issue Queue Number of matching 2-bit groups % of total cases SPEC2000 Average

13 09/16/2002 ICCD 2002 Energy Dissipation in Various Matching Cases

14 09/16/2002 ICCD 2002 Main Results Two-stage domino-style comparator: 65% comparator energy reduction in the issue queue About 25% increase in response time PLSSC: 75% comparator energy reduction in the issue queue Slight improvement in response time PLSSC is the design of choice for 8-bit comparands. Domino-style design is a more scalable solution.


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