Presentation is loading. Please wait.

Presentation is loading. Please wait.

Sequentiële schakelingen n Toestand uitgang bepaald door: –ingangen; –vorige toestand uitgang.

Similar presentations


Presentation on theme: "Sequentiële schakelingen n Toestand uitgang bepaald door: –ingangen; –vorige toestand uitgang."— Presentation transcript:

1 Sequentiële schakelingen n Toestand uitgang bepaald door: –ingangen; –vorige toestand uitgang

2 Flipflops/latches n Set-Reset latch n D-latch n D-flipflop n JK-flipflop

3 Set-Reset latch set reset 0 0

4 Set-Reset latch set reset 0 0 1 1

5 Set-Reset latch set reset 0 1

6 Set-Reset latch set reset 0 1 1 1 0

7 Set-Reset latch set reset 1 0 0 1 1

8 Set-Reset latch set reset 1 1

9 Set-Reset latch set reset 1 1

10 Set-Reset latch set reset 1 1 1

11 Set-Reset latch set reset 1 1 1 10

12 Set-Reset latch set reset 1 1 0 01

13 Set-Reset latch set reset 1 1 q q

14 set Set-Reset latch reset 1 1 q q

15 set D-latch reset

16 set D-latch reset 1 1 1 1 0 0

17 set D-latch reset 1 1 1 1 0 0 0 1

18 set D-latch reset 0 1 1 0

19 set D-latch reset 0 1 1 0 1 1 0 0

20 set D-latch reset x 0

21 set D-latch reset x 0 1 1

22 D-flipflop edge

23 Flank- of edgetriggered n Kloksignaal time positive edgenegative edge level

24 Twee manieren van “triggeren” n “level triggered”: latches n “edge triggered”: flipflops

25 JK-flipflop CLOCK J K & & 11 1 1D C1 Q Q 1J 1K Q Q J K C1CLK D B A

26 JK-flipflop CLOCK J K & & 11 1 1D C1 Q Q 1J 1K Q Q J K C1CLK 0 0 q q B A D

27 JK-flipflop CLOCK J K & & 11 1 1D C1 Q Q 1J 1K Q Q J K C1CLK 0 0 q q 0 q q 1

28 JK-flipflop CLOCK J K & & 11 1 1D C1 Q Q 1J 1K Q Q J K C1CLK 1 1 q q ? ? ?

29 JK-flipflop CLOCK J K & & 11 1 1D C1 Q Q 1J 1K Q Q J K C1CLK 1 1 q q 0 q q

30 Frequentiedeler 1 1J 1K C1 Q 1 1 1J 1K C1 Q 1 1 1J 1K C1 Q 1 1 1J 1K C1 Q 1 CLOCK Q0Q0 Q1Q1 Q2Q2 Q3Q3 Q3Q3 Q2Q2 Q1Q1 Q0Q0

31 Pauze 13.30 uur vervolg college over: DRAM SRAM

32 Static RAM cell (SRAM)

33 5 Volt 0 Volt 5 V 1 k  1 M  5 Volt 0 Volt 0 V 1 k  1 

34 Static RAM cell (SRAM)

35 Dynamic RAM cell (DRAM) 10 -15 F

36 16 Megabit DRAM (4M *4)

37 Pin configuration 16 M-bit DRAM

38 512 * 512 *1* 8 262.144 * 8 bits  256 kByte DRAM

39 The Memory Hierarchy Edge triggered flipflops SRAM DRAM


Download ppt "Sequentiële schakelingen n Toestand uitgang bepaald door: –ingangen; –vorige toestand uitgang."

Similar presentations


Ads by Google