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Best Practices: Operations in a Fabless Startup Gina Gloski President Semiconductor Operations Consulting.

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Presentation on theme: "Best Practices: Operations in a Fabless Startup Gina Gloski President Semiconductor Operations Consulting."— Presentation transcript:

1 Best Practices: Operations in a Fabless Startup Gina Gloski President Semiconductor Operations Consulting

2 March 2006 Semiconductor Operations Consulting2 Topics Planning for Operations Resource Requirements Fixed Operations Costs Variable Cost Factors Key Things to Remember

3 March 2006 Semiconductor Operations Consulting3 Planning For Operations First step: Establish a baseline Where is your company/product in the design cycle? Specification/MRD RTL Netlist Working prototypes

4 March 2006 Semiconductor Operations Consulting4 Planning For Operations At Specification time Baseline development and material costs Research foundry capabilities to support product performance and IP requirements Determine development and prototype cycle time and develop contingency plans Respin Redesign

5 March 2006 Semiconductor Operations Consulting5 Planning For Operations At RTL time Must have completed all items from previous slide… or you are already behind the curve! Finalize DFT strategy Evaluate internal or external test program development Choose foundry partner and begin relationship building Revise cost and cycle time assumptions

6 March 2006 Semiconductor Operations Consulting6 Planning For Operations At Netlist time All previous activities completed Select package, assembly and test/test development partners and begin managing these relationships Revise cost and cycle time assumptions Evaluate yield and WIP data management systems Define operations system requirements Develop qualification and characterization plan and partners Evaluate and set document control system Begin customization of operations forms and key procedures

7 March 2006 Semiconductor Operations Consulting7 Planning For Operations At Working Prototypes time Ensure all previous steps completed Update material costs with refined test and assembly assumptions Select yield and WIP data management methodology Execute product qualification plan Execute characterization plan Complete key operating procedures Develop or buy forecast, WIP, order management and planning process and management tools Exit strategy of public offering vs buy out factor in system selections

8 March 2006 Semiconductor Operations Consulting8 Planning For Operations Second step: Define requirements to support your end product Are you shipping a reference design or software with each chip? Are your targeted customers going to require early ISO 9000/2000 certification? Software control – you need a document control system at RTL time Need quality/manufacturing engineer to support component, PCB and supplier selection at time of RTL

9 March 2006 Semiconductor Operations Consulting9 Planning For Operations Are you utilizing alternative fab processes? RF GaAs SiGe These take longer to debug and qualify and fewer skilled people in marketplace for design Manufacturing supplier relationships and product support requirements take longer to refine

10 March 2006 Semiconductor Operations Consulting10 Planning For Operations Third step: Product portfolio breadth How many designs or new tapeouts are anticipated each year? 5+ design tapeouts per year may justify design tool expenditures and in house operations team 3-5 tapeouts – portions of operations may be outsourced to reduce cost and underutilization of resources For 1-3 design starts per year, consider outsourcing both physical design and operations Determine probability of first time working prototype Be Realistic!

11 March 2006 Semiconductor Operations Consulting11 Resource Requirements Staffing First hire: hands on VP/Director of Operations at RTL time Plan on 3 months for hiring process VP/Director accountable for Staffing up group Supplier relationship development, pricing negotiations and cost model With engineering manager supplier selection System requirements Positions to be filled by time of production: product engineer, test engineer (if internal test development), quality engineer/document control, supply planner/buyer/order management

12 March 2006 Semiconductor Operations Consulting12 Resource Requirements Product Engineer Characterization plan and execution Yield Management strategy DFT Strategy

13 March 2006 Semiconductor Operations Consulting13 Resource Requirements Planner/Buyer/Customer Service (at production ramp time) Accept and place purchase orders Contract reviews Manage logistics of shipment to end customers Forecast management Build plan development

14 March 2006 Semiconductor Operations Consulting14 Resource Requirements Quality Engineer (at netlist time) Document control development and management (especially important if shipping software and/or ISO compliance) Supplier quality management Customer quality management Component qualification plan and execution

15 March 2006 Semiconductor Operations Consulting15 Fixed Operations Costs What are the fixed cost assumptions? (based on the number of tapeouts annually) Mandatory to model the following costs: Labor International travel and communications IT support personnel IT systems and maintenance Transportation and insurance Inventory carrying costs Facilities

16 March 2006 Semiconductor Operations Consulting16 Operations Cost – when in Production Essential Infrastructure Captive Operations Labor: 4-5 Perfect-fit employees, office space, travel, salary, benefits, computers, software $800K to $1M Annually Shipping logistics and insurance0.3% of COGS IT Infrastructure: Servers, 1 Perfect-fit IT employee, supply chain and logistics software, document control, yield management, maintenance and support $200K to $500K NRE Up to ½ of NRE annually

17 March 2006 Semiconductor Operations Consulting17 Staffing If you have flip chip or thermal or electrical enhancements, add one packaging expert expect to pay at least ½ of package development cost for characterization If analog content is greater than 20%, add one test engineer and plan 6 months to find If using alternate fab processes, add at least one process engineer Remember the risk if you have only one expert in any given area… What will you do if they leave? Fixed Operations Cost

18 March 2006 Semiconductor Operations Consulting18 Variable Cost Factors Material Cost Modeling Available at time of Print IC Knowledge Corp: Current Year IC Cost Model: Use FSA wafer pricing data and build your own

19 March 2006 Semiconductor Operations Consulting19 Variable Cost Factors NRE Masks/Merge if IP Load boards (3 per product) Probe cards (3 per product) Burn-In boards Sockets Proto wafers (12 wafers) Corner lot (12 wafers) Sort, package, assembly, test of qualification and corner lots Qualification testing cost (Life test, ESD, Latch Up, Temp Cycle) Tester time rental or supplier test program development cost Package design and tooling Ball placement tool (BGA only)

20 March 2006 Semiconductor Operations Consulting20 Variable Cost Factors Wafer Cost Process technology (nPoly layers, xMetal layers) Die Size Xeff (mm) = X + adj. factor for scribe lines (120 to 250 Die Size Yeff (mm) = Y + adj. factor for scribe lines Die Area (mm^2) Gross Die Epi/LV/LPa or other custom process adders Backgrind cost/wafer Yield parameters: Process complexity n Effective do (/in^2) w/small die yield adjustment

21 March 2006 Semiconductor Operations Consulting21 Gross Die Formula Each foundry has their own gross die formula General formula: Gross dies per wafer = (area of wafer)/(area of die) - Pi*(wafer diameter)/(sqrt(2*die area)) Variable Cost Factors

22 March 2006 Semiconductor Operations Consulting22 Variable Cost Factors Defect Density Projections Poisson's yield model: Yield = exp(-A*D0) Both defect density and process complexity lumped into one parameter D0. Negative binomial model: Yield = 1/((1+A*D0)^n) Defect density and process complexity separated out into two parameters. Murphy's yield model: Yield = ((1-exp(-A*D0))/A*D0)^2 This one is not as popular as the previous two.

23 March 2006 Semiconductor Operations Consulting23 Defect Density Projections (continued) If using 30% or more SRAM effective defect density is higher than logic and must be adjusted Analog IP are less defect density sensitive, but difficult to predict using defect-based yield models Variable Cost Factors

24 March 2006 Semiconductor Operations Consulting24 Variable Cost Factors Assembly Cost Package type Body size Thickness Lead spacing Ball/pin pitch Pin count Number of substrate layers Number of bond wires Assembly yield Electrical characteristics Thermal characteristics ( JA ) and analysis Cavity up or down or flip chip

25 March 2006 Semiconductor Operations Consulting25 Variable Cost Factors Test Cost Tester cost/hour (platform required) Probe testing temperature Final test temperature Handler index time Prober index time Utilization factor at sort Utilization factor at final test Final test time in CPU seconds Wafer sort time in CPU seconds Final test yield Wafer sort yield (in addition to defect density)

26 March 2006 Semiconductor Operations Consulting26 Variable Cost Factors Overhead Cost Operations overhead $ (% of units manufactured) IT overhead (systems and people to support operations)

27 March 2006 Semiconductor Operations Consulting27 Variable Cost Factors Production Ramp Cycles of Learning Whatever production cost is, plan for at least 2X cost for first 3 months of production. Need to optimize: Yield Test time Cycle time Can be longer based on volume ramp. Typically need 5 wafer lots at least for digital products Don t underestimate cost and labor to get product out Need slush fund for debug (ebeam, FIB) Model risk buy contingencies Can you afford all risk buy material to be scrapped at your cost?

28 March 2006 Semiconductor Operations Consulting28 Key Things To Remember Supplier quotes Ensure all necessary steps included Scan, bake, dry pack 5V tolerant mask step Package cost factored by number of bond wires Development of sort, final test and QA programs Realistic start up and production final test time, including set up and index time (understand test cost models)

29 March 2006 Semiconductor Operations Consulting29 Key Things To Remember Transportation costs for prototypes, preproduction and shipping to assembly (Re: variable costs) Import/Export classification (DES encryption can add 4 month to product classification time) Product insurance

30 March 2006 Semiconductor Operations Consulting30 Key Things To Remember Can you afford the operational people if your first product needs to be redesigned? This is when most companies need to have a Reduction in Force. Minimize this negative impact Prepare contingency modeling for time and cost if redesign or respin is needed IT infrastructure Reverse bill of materials needs tier II ERP vendor as a minimum Yield management model is required, you own it if you own operations Reporting, backlog, costed BOM is critical if you own operations Document Control needs to be put in early, low cost, but trains everyone to control Docs

31 March 2006 Semiconductor Operations Consulting31 Key Things to Remember Be clear on the core skills of your company: Physical design and operations ownership Getting the right product to market Don t underestimate supply relationship building There is a lot of trust involved in this business Don t start too late – you will not recover! Cash conservation and contingency planning are critical Where are your funding dollars best spent?

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