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Orientation of Subject By:- Mr.G.P SINGH Asst.Prof. Faculty of Computer Application,Gharaun Campus,Mohali 111/10/2013.

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Presentation on theme: "Orientation of Subject By:- Mr.G.P SINGH Asst.Prof. Faculty of Computer Application,Gharaun Campus,Mohali 111/10/2013."— Presentation transcript:

1 Orientation of Subject By:- Mr.G.P SINGH Asst.Prof. Faculty of Computer Application,Gharaun Campus,Mohali 111/10/2013

2 INTRODUCTION TO MICROPROCESSOR MCA-205 (N2) Internal Assessment: 40 External Assessment: 60 Faculty of Computer Application,Gharaun Campus,Mohali 211/10/2013

3 CONTENTS Section A Introduction to Microprocessor, its historical background and Microprocessor applications. INTEL 8085 : Microprocessor Architecture and its operations, 8085 MPU and its architecture, 8085 instruction cycle and timing diagram, Memory read and Memory Write operations, Instructions for 8085: Data movement, Arithmetic and logic; and branch control instructions Section B INTEL 8086 : Introduction, 8086Architecture, real and Protected mode, Memory Addressing, Memory Paging, Addressing Modes. Pin diagram of 8086, clock generator (8284A) Section C Various types of instructions: Data movement, Arithmetic and logic; and program control. Section D Interrupts: Introduction, 8257 Interrupt controller, basic DMA operation and 8237 DMA Controller, Arithmetic coprocessor, 80X87 Architecture,., RISC v/s CISC processors. Faculty of Computer Application,Gharaun Campus,Mohali 311/10/2013

4 REFERENCES: B. Brey The Intel microprocessors 8086/8086, 80186/80188, 80286,80386, Pentium pro processor Architecture,Programming and interfacing 4th Edition. B. Ram Fundamentals of microprocessors and HI microcomputers,Dhanpat RaiPublication. Ramesh S. Gaonkar Microprocessor Architecture, Programming and Applications with 8085,4th edition, Penram International Publishing (India) Faculty of Computer Application,Gharaun Campus,Mohali 411/10/2013

5 Practical Hardware Lab – I(Microprocessor) MCA-207 (N2) Internal Assessment 40 External Assessment 60 Using 8085 and 8086 microprocessor kits do the following programs: To examine and modify the contents of a register and memory location. 2. To add two hexadecimal nos. 3. To subtract two hexadecimal nos. 4. To add two hexadecimal nos. The result should not be greater than To add two sixteen bit nos. 6. To subtract two sixteen bit nos. 7. For addition of 8 bit no series neglecting the carry generated. 8. To separate hexadecimal number into two digits(Breaking the byte into two nibbles) To add two binary nos each 8 bit long. 2 To add two binary nos each 8 bit long. 3. To multiply two binary nos. 4.To find the maximum no in a given string (16 bytes long) and store it in a particular location. 5.To find the minimum no in a given string (16 bytes long) and store it in a particular location. 6.To sort a string of a no of bytes in descending order. 7.To multiply an ASCII string of eight numbers by single ASCII digit. 8.To calculate the no. of bytes in a string starting from a particular location up to an Identifier (data byte) placed in AL register. Store the actual count in a particular memory Location. Faculty of Computer Application,Gharaun Campus,Mohali 511/10/2013

6 What well Study in This? Theory-Part 1. Microprocessors Origin. 2. Various Processors available till date. 3. Application in real world.i.e daily life examples.(Case Studies )…Traffic light,etc. 4. Programming in ALP(in Practical using 8085 and 8086 Kit.) 5. Job Prospects??????????????? Faculty of Computer Application,Gharaun Campus,Mohali 611/10/2013

7 Practical Part 1. Programming in ALP(using 8085 and 8086 Kit.) Faculty of Computer Application,Gharaun Campus,Mohali 711/10/2013

8 INTRODUCTION COMPUTER GENERATIONS:- First Generation Computers( ) VACUUM TUBES.e.g.:-ENIAC(Electronic Numerical Integrator and Calculator) EDVAC:-Electronic discrete Variable Automatic Computer. EDSAC: Electronic Delay Storage Automatic Computer. UNIVAC-1: Universal Accounting Computer Setup. Faculty of Computer Application,Gharaun Campus,Mohali 811/10/2013

9 COMPUTER GENERATIONS Second Generation( ) Transistors.e.g IBM 1620,IBM 1401,CDC 3600 Programming Languages:- COBOL,FORTAN. Faculty of Computer Application,Gharaun Campus,Mohali 911/10/2013

10 COMPUTER GENERATIONS THIRD GENERATION( ) INTEGRATED CIRCUITS:- (CHIPS),(Registers,capacitors,Transistors) IBM-360,ICL-1900,IBM-370,VAX-750. Programming Language:- BASIC Faculty of Computer Application,Gharaun Campus,Mohali 1011/10/2013

11 COMPUTER GENERATIONS FOURH GENERATION(1971-Present) MICROPROCESSORS. LSIC(Large Scale Integrated Circuits) built on single Chip called as MICROPROCESSORS. VLSIC(Very Large scale integrated Circuits) E.g.:- PC. Faculty of Computer Application,Gharaun Campus,Mohali 1111/10/2013

12 COMPUTER GENERATIONS FIFTH GENERATION:-PRESENT and BEYOND ARTIFICIAL INTELLIGENCE. YEAR-1990-Fifth Generation Computers Started. QUANTUM COMPUTATION,MOLECULAR,NANOTECHNOLOGY. Goal:- To develop computer that respond to natural language input and are capable of learning and self-organization. Faculty of Computer Application,Gharaun Campus,Mohali 1211/10/2013

13 HISTORY OF MICROPROCESSORS Fairchild Semiconductors (founded in 1957) invented the first IC in In 1968, Robert Noyce, Gordan Moore, Andrew Grove resigned from Fairchild Semiconductors They founded their own company Intel (Integrated Electronics). Intel grown from 3 man start-up in 1968 to industrial giant by It had 20,000 employees and $188 million revenue. Faculty of Computer Application,Gharaun Campus,Mohali 1311/10/2013

14 Generation of Microprocessor FIRST GENERATION MICROPROCESSOR:- Ted Hoff of INTEL Corporation developed Controlled Processor in Intel 4004:- Introduced in It was the first microprocessor by Intel It was a 4-bit MP. PMOS Technology. Device: CALCULATOR Faculty of Computer Application,Gharaun Campus,Mohali 1411/10/2013

15 Generation of Microprocessor Intel 4040:- Introduced in It was also 4-bit MP. Faculty of Computer Application,Gharaun Campus,Mohali 1511/10/2013

16 Generation of Microprocessor Faculty of Computer Application,Gharaun Campus,Mohali INTEL-8008 Introduced in It was first 8-bit MP. Could execute 50,000 instructions per second 1611/10/2013

17 Generation of Microprocessor First Generation Summary MICRPPROCESSORWORD SIZE INTEL 4004 & bit FAIRCHILD PPS-254-bit NATIONAL IMP-44-bit ROCKWELL PPS-44 bit MICROSYSTEM4-bit INYEL bit NATIONAL IMP-88-bit ROCKWELL PPS8-bit AMI bit MOSTEK bit Faculty of Computer Application,Gharaun Campus,Mohali 1711/10/2013

18 Generation of Microprocessor 2 nd Generation Started in Year Intel 8080 It was also 8-bit MP. Was 10 times faster than Could execute 5,00,000 instructions per second NMOS TECHNOLOGY. Faculty of Computer Application,Gharaun Campus,Mohali 1811/10/2013

19 Generation of Microprocessor 2 nd Generation Faculty of Computer Application,Gharaun Campus,Mohali Introduced in It was also 8-bit MP. Could execute 7,69,230 instructions per second. It could access 64 KB of memory. It had 256 instructions. Over 100 million copies were sold Intel /10/2013

20 Generation of Microprocessor 2 nd Generation FEATURES OF SECOND GENERATION:- LARGE CHIP SIZE(170*200) WITH 40 PINS. MORE CHIP ON DECODING CIRCUITS. ABLITY TO ADDRESS LARGE MEMORY SPACE(64KB) AND I/O PORTS (256). MORE POWERFUL INSTRUCTION SET. Dissipate less power. Better INTERUPT HANDLING FACILITIES. CYCLE TIME REDUCED TO HALF (1.3 TO 9 n.s) LESS SUPPORT CHIPS REQUIRED. USED SINGLE POWER SUPPLY. Faculty of Computer Application,Gharaun Campus,Mohali 2011/10/2013

21 Generation of Microprocessor 2 nd Generation Second Generation Summary MICROPROCESSORWORD SIZE INTEL 8080/80858-bit FAIRCHILD F88-bit NATIONAL CMP-48 bit MOTOROLA bit RCA COSMAC8 bit MOS TECH bit SIGNETICS bit ZILOG Z-808 bit INTERSIL bit TOSHIBA TICS-1212 bit Faculty of Computer Application,Gharaun Campus,Mohali 2111/10/2013

22 Generation of Microprocessor 3 rd Generation Intel 8086 Introduced in It was first 16-bit MP. Could execute 2.5 million instructions /sec. It could access 1 MB of memory. It had 22,000 instructions. It had Multiply and Divide instructions. HMOS TECHNOLOGY.(high density short channel MOS) Faculty of Computer Application,Gharaun Campus,Mohali 2211/10/2013

23 Generation of Microprocessor 3 rd Generation Intel 8088 Introduced in It was also 16-bit MP. Could execute 2.5 million instructions per second. It could access 1 MB of memory. It had 22,000 instructions. It had Multiply and Divide instructions Faculty of Computer Application,Gharaun Campus,Mohali 2311/10/2013

24 Generation of Microprocessor 3 rd Generation Faculty of Computer Application,Gharaun Campus,Mohali Introduced in They were 16-bit MPs. They had additional components like: Interrupt Controller Clock Generator Local Bus Controller Counters Intel & /10/2013

25 Generation of Microprocessor 4 th Generation Intel Introduced in It was 16-bit MP. It could address 16 MB of memory. It could execute 4 million instructions per second. Its clock speed was 8 MHz Faculty of Computer Application,Gharaun Campus,Mohali 2511/10/2013

26 Generation of Microprocessor 4 th Generation Intel Introduced in It was first 32-bit MP. It could address 4 GB of memory. Different versions: SX SL / SLC EX Faculty of Computer Application,Gharaun Campus,Mohali 2611/10/2013

27 Generation of Microprocessor 4 th Generation Introduced in It was also 32-bit MP. It had 1.2 million transistors. Cache memory was introduced Faculty of Computer Application,Gharaun Campus,Mohali Intel /10/2013

28 Generation of Microprocessor 5 th Generation(1993-onwards) Intel Pentium Introduced in March 22,1993. It was also 32-bit MP. It was originally named Could execute 110 million instructions per sec. Cache memory: 8 KB for instructions. 8 KB for data Faculty of Computer Application,Gharaun Campus,Mohali 2811/10/2013

29 Generation of Microprocessor THE PENTIUM PRO Intel Pentium Pro Introduced in It was also 32-bit MP. It had 21 million transistors Cache memory: 8 KB for instructions. 8 KB for data. It had L2 cache of 256 KB.(Level 2) L2 cache memory, also called the secondary cache, resides on a separate chip from the microprocessor chipchip Faculty of Computer Application,Gharaun Campus,Mohali 2911/10/2013

30 Generation of Microprocessor THE PENTIUM SERIES Intel Pentium II Introduced in It was also 32-bit MP. Could execute 333 million instructions per second. MMX technology was supported.(Multi-Media-eXtension) L2 cache & processor were on one circuit. Level 3 cache is now the name for the extra cache built into motherboards between the microprocessor and the main memory.cache motherboardsmain memory Faculty of Computer Application,Gharaun Campus,Mohali 3011/10/2013

31 Generation of Microprocessor THE PENTIUM SERIES Intel Pentium II Xeon Introduced in It was also 32-bit MP. It was designed for servers. L1 cache of 32 KB & L2 cache of 512 KB, 1MB or 2 MB. It could work with 4 Xeons in same system. Faculty of Computer Application,Gharaun Campus,Mohali 3111/10/2013

32 Generation of Microprocessor THE PENTIUM SERIES Intel Pentium III Introduced in It was also 32-bit MP. Its clock speed was 1GHz. Faculty of Computer Application,Gharaun Campus,Mohali 3211/10/2013

33 Generation of Microprocessor THE PENTIUM SERIES Intel Pentium IV Introduced in It was also 32-bit MP. L1 cache was of 32 KB & L2 cache of 256 KB. It had 42 million transistors. All internal connections were made from aluminum to copper Faculty of Computer Application,Gharaun Campus,Mohali 3311/10/2013

34 Generation of Microprocessor THE PENTIUM SERIES Intel Dual Core Introduced in It was 32-bit or 64-bit MP. It had two cores. It supported SMT technology. SMT: Simultaneously Multi-Threading E.g.: Adobe Photoshop supported SMT Faculty of Computer Application,Gharaun Campus,Mohali 3411/10/2013

35 Generation of Microprocessor THE PENTIUM SERIES Intel Core 2 Duo Introduced in It was 32-bit or 64-bit MP Faculty of Computer Application,Gharaun Campus,Mohali 3511/10/2013

36 The Intel family of Processors Intel was founded on July 18, 1968, as Integrated Electronics Corporation, is based in Santa Clara, California, USA.Santa ClaraCalifornia Gordon Moore and Robert Noyce Faculty of Computer Application,Gharaun Campus,Mohali 3611/10/2013

37 OTHER PROCESSORS Elbrus E2K(Elbrus 2000):- It has been developed by МЦСТ (MZST, Moscow center for SPARC-technology).МЦСТ Elbrus:- ExpLicit Basic Resources Utilization Scheduling.(named after Mount Elbrus in russia)Mount Elbrus Soviet supercomputer systems developed by Lebedev Institute of Precision Mechanics and Computer Engineering Sovietsupercomputer Lebedev Institute of Precision Mechanics and Computer Engineering Faculty of Computer Application,Gharaun Campus,Mohali 3711/10/2013

38 Advanced Micro Devices, Inc. (AMD) It is an American multinational semiconductor company based in Sunnyvale, California USA.semiconductor Sunnyvale, California products include microprocessors, motherboard chipsets, embedded processors and graphics processors for servers, workstations and personal computers, and processor technologies for handheld devices, digital television, automobiles, game consoles, and other embedded systems applications.microprocessorsmotherboardchipsetsembedded processorsgraphics processorsserversworkstationshandheld devicesdigital televisionautomobilesgame consoles embedded systems Faculty of Computer Application,Gharaun Campus,Mohali 3811/10/2013

39 List of AMD microprocessors Faculty of Computer Application,Gharaun Campus,Mohali AMD AM9080ADC / C8080A), /10/2013

40 List of AMD microprocessors Faculty of Computer Application,Gharaun Campus,Mohali AMD D /10/2013

41 List of AMD microprocessors Faculty of Computer Application,Gharaun Campus,Mohali AMD K /10/2013

42 List of AMD microprocessors Faculty of Computer Application,Gharaun Campus,Mohali K6 (Model 6) /10/2013

43 List of AMD microprocessors Faculty of Computer Application,Gharaun Campus,Mohali K6 "Little Foot" (Model 7) 4311/10/2013

44 List of AMD microprocessors Faculty of Computer Application,Gharaun Campus,Mohali Athlon (Thunderbird (T-Bird ) June 5, /10/2013

45 List of AMD microprocessors Faculty of Computer Application,Gharaun Campus,Mohali Athlon XP/MPPalomino October 9, /10/2013

46 List of AMD microprocessors Faculty of Computer Application,Gharaun Campus,Mohali Thoroughbred (T-Bred ) 10 June /10/2013

47 List of AMD microprocessors Faculty of Computer Application,Gharaun Campus,Mohali AMD Duron "Spitfire" 600MHz CPU June 19, /10/2013

48 List of AMD microprocessors Faculty of Computer Application,Gharaun Campus,Mohali Sempron (Barton ) July /10/2013

49 APPLICATIONS OF MICROPROCESSOR 1. Microprocessors used in everything from the smallest embedded systems and handheld devices to the largest mainframes and supercomputers.embedded systemshandheld devicesmainframessupercomputers 2. Embedded system:- An embedded system is a computer system designed to perform one or a few dedicated functions often with real-time computing constraints. It is embedded as part of a complete device often including hardware and mechanical parts. By contrast, a general-purpose computer, such as a personal computer (PC), is designed to be flexible and to meet a wide range of end-user needs. Embedded systems control many devices in common use today.computer systemreal-time computingpersonal computer Embedded systems are controlled by one or more main processing cores that are typically either microcontrollers or digital signal processors (DSP).The key characteristic, however, is being dedicated to handle a particular task, which may require very powerful processors.microcontrollersdigital signal processors Faculty of Computer Application,Gharaun Campus,Mohali 4911/10/2013

50 APPLICATIONS OF MICROPROCESSOR For example, air traffic control systems may usefully be viewed as embedded, even though they involve mainframe computers and dedicated regional and national networks between airports and radar sites (each radar probably includes one or more embedded systems of its own).air traffic controlmainframe computers Faculty of Computer Application,Gharaun Campus,Mohali 5011/10/2013

51 APPLICATIONS OF MICROPROCESSOR The embedded system is dedicated to specific tasks, design engineers can optimize it to reduce the size and cost of the product and increase the reliability and performance. Embedded systems range from portable devices such as digital watches and MP3 players, to large stationary installations like traffic lights, factory controllers, or the systems controlling nuclear power plants. Complexity varies from low, with a single microcontroller chip, to very high with multiple units, peripherals and networks mounted inside a large chassis or enclosure.digital watches MP3 playerstraffic lightsfactory controllersnuclear power plantsmicrocontrollerchassis Faculty of Computer Application,Gharaun Campus,Mohali 5111/10/2013

52 APPLICATIONS OF MICROPROCESSOR The Intel Core i7 microprocessor in aerospace and defense applications. The Intel Core i7 microprocessor in aerospace and defense applications Today, micro processors are included in almost any electronically device: computers, and any computer-like device such as mobile phones, PDAs, digital video cameras or recorders, digital cameras, etc. Microprocessors are also used in many cars (or: vehicles in general), domestic appliances like washing machines, refrigerators, microwave ovens or coffee makers. Basically, almost any electronic device, or device that uses electronics, employs some form of a micro processor. The group of devices using micro processors even extends to those devices that were traditionally pure electrical, or electro-mechanic, devices such as light switches or light bulb holders, thermostatic radiator valves. Faculty of Computer Application,Gharaun Campus,Mohali 5211/10/2013

53 APPLICATIONS OF MICROPROCESSOR iPhone :- There are actually 2 microprocessors in the iPhone: The processor and the baseband. The baseband controls wireless functions of the iPhone such as Bluetooth and telephone connection. This processor is a resource to the main processor which is used to control the user interface and higher-level systems of the Phone, such as applications that the user is likely to interact with. Faculty of Computer Application,Gharaun Campus,Mohali 5311/10/2013

54 Difference between a microprocessor and a microcontroller? A microcontroller is a specialized form of microprocessor that is designed to be self-sufficient and cost-effective, where a microprocessor is typically designed to be general purpose (the kind used in a PC). Microcontrollers are frequently found in automobiles, office machines, toys, and appliances. The microcontroller is the integration of a number of useful functions into a single IC package. These functions are: a) The ability to execute a stored set of instructions to carry out user defined tasks. b) The ability to be able to access external memory chips to both read and write data from and to the memory. Basically, a microcontroller is a device which integrates a number of the components of a microprocessor system onto a single microchip. Faculty of Computer Application,Gharaun Campus,Mohali 5411/10/2013

55 Microcontroller combines onto the same microchip. The CPU core (microprocessor). Memory (both ROM and RAM). Some parallel digital I/O Also, a microcontroller is part of an embedded system, which is essentially the whole circuit board. Faculty of Computer Application,Gharaun Campus,Mohali 5511/10/2013

56 BLOCK DIAGRAM OF INTEL 8085 Faculty of Computer Application,Gharaun Campus,Mohali 5611/10/2013

57 Introduction to 8085 Introduced in It is 8-bit MP. It is a 40 pin dual-in-line chip. It uses a single +5V supply for its operations. Its clock speed is about 3MHz. Faculty of Computer Application,Gharaun Campus,Mohali 5711/10/2013

58 Block Diagram of 8085 Faculty of Computer Application,Gharaun Campus,Mohali 5811/10/2013

59 Three Units of 8085 Processing Unit Instruction Unit Storage and Interface Unit Faculty of Computer Application,Gharaun Campus,Mohali 5911/10/2013

60 Processing Unit Arithmetic and Logic Unit Accumulator Status Flags Temporary Register Faculty of Computer Application,Gharaun Campus,Mohali 6011/10/2013

61 Instruction Unit Instruction Register Instruction Decoder Timing and Control Unit Faculty of Computer Application,Gharaun Campus,Mohali 6111/10/2013

62 Storage and Interface Unit General Purpose Registers Stack Pointer Program Counter Increment/Decrement Register Address Latch Address/Data Latch Faculty of Computer Application,Gharaun Campus,Mohali 6211/10/2013

63 Three Other Units Interrupt Controller Serial I/O Controller Power Supply Faculty of Computer Application,Gharaun Campus,Mohali 6311/10/2013

64 Accumulator It the main register of microprocessor. It is also called register A. It is an 8-bit register. It is used in the arithmetic and logic operations. It always contains one of the operands on which arithmetic/logic has to be performed. After the arithmetic/logic operation, the contents of accumulator are replaced by the result. Faculty of Computer Application,Gharaun Campus,Mohali 6411/10/2013

65 Arithmetic & Logic Unit (ALU) It performs various arithmetic and logic operations. The data is available in accumulator and temporary/general purpose registers. Arithmetic Operations: – Addition, Subtraction, Increment, Decrement etc. Logic Operations: – AND, OR, X-OR, Complement etc. Faculty of Computer Application,Gharaun Campus,Mohali 6511/10/2013

66 Temporary Register It is an 8-bit register. It is used to store temporary 8-bit operand from general purpose register. It is also used to store intermediate results. Faculty of Computer Application,Gharaun Campus,Mohali 6611/10/2013

67 Status Flags Status Flags are set of flip-flops which are used to check the status of Accumulator after the operation is performed. Faculty of Computer Application,Gharaun Campus,Mohali 6711/10/2013

68 Status Flags S=Sign Flag Z=Zero Flag AC=Auxiliary Carry Flag P=Parity Flag CY=Carry Flag Faculty of Computer Application,Gharaun Campus,Mohali 6811/10/2013

69 Status Flags Sign Flag (S): – It tells the sign of result stored in Accumulator after the operation is performed. – MSB(7 th bit) of 8 bit number will tell sign. Rest of bits will tell magnitude.(same in case of 16 bit or 32 bit). – So numbers can be used in the range -128 to 127. – If result is –ve i.e MSB is 1, sign flag is set (1). – If result is +ve i.e MSB is 0, sign flag is reset (0). Faculty of Computer Application,Gharaun Campus,Mohali 6911/10/2013

70 Status Flags Zero Flag (Z): – It tells whether the result stored in Accumulator is zero or not after the operation is performed. – If result is zero, zero flag is set (1). – If result is not zero, zero flag is reset (0). – Hexadecimal: B3+4D=00, Carry:- 1 – SO CARRY FLAG (CY) IS ALSO SET TO 1. Faculty of Computer Application,Gharaun Campus,Mohali 7011/10/2013

71 Status Flags Auxiliary Carry Flag (AC): – It is used in BCD operations. – ADD CB+E9=B4. – There is carry from 3 rd bit to 4 th bit. So AC is set to 1. – The counting stars from zero. – If there is carry in BCD addition, auxiliary carry is set (1). – If there is no carry, auxiliary carry is reset (0). Faculty of Computer Application,Gharaun Campus,Mohali 7111/10/2013

72 Status Flags Parity Flag (P): – It tells the parity of data stored in Accumulator after execution of airthmatic or logical operations.. – It is defined as number of 1s present in the accumulator. – If parity is even, parity flag is set (1). – If parity is odd, parity flag is reset (0). Faculty of Computer Application,Gharaun Campus,Mohali 7211/10/2013

73 Program Status Word (PSW) The contents of Accumulator and Status Flags clubbed together is known as Program Status Word (PSW). It is a 16-bit word. Faculty of Computer Application,Gharaun Campus,Mohali 7311/10/2013

74 Instruction Register It is used to hold the current instruction which the microprocessor is about to execute. It is an 8-bit register. Faculty of Computer Application,Gharaun Campus,Mohali 7411/10/2013

75 Instruction Decoder It interprets the instruction stored in instruction register. It generates various machine cycles depending upon the instruction. The machine cycles are then given to the Timing and Control Unit. Faculty of Computer Application,Gharaun Campus,Mohali 7511/10/2013

76 Timing and Control Unit It controls all the operations of microprocessor and peripheral devices. Depending upon the machine cycles received from Instruction Decoder, it generates 12 control signals: – S 0 and S 1 (Status Signals). – ALE (Address Latch Enable). Faculty of Computer Application,Gharaun Campus,Mohali 7611/10/2013

77 Timing and Control Unit – RD (Read, active low). – WR (Write, active low). – IO/M (Input-Output/Memory). – READY – RESET IN – RESET OUT – CLK OUT – HOLD and HLDA Faculty of Computer Application,Gharaun Campus,Mohali 7711/10/2013

78 General Purpose Registers There are 6 general purpose registers, namely B, C, D, E, H, L. Each of the them is 8-bit register. They are used to hold data and results. To hold 16-bit data, combination of two 8-bit registers can be used. This combination is known as Register Pair. The valid register pairs are: – B – C, D – E, H – L. Faculty of Computer Application,Gharaun Campus,Mohali 7811/10/2013

79 Program Counter It is used to hold the address of next instruction to be executed. It is a 16-bit register. The microprocessor increments the value of Program Counter after the execution of the current instruction, so that, it always points to the next instruction. Faculty of Computer Application,Gharaun Campus,Mohali 7911/10/2013

80 Stack Pointer It holds the address of top most item in the stack. It is also 16-bit register. Any portion of memory can be used as stack. Faculty of Computer Application,Gharaun Campus,Mohali 8011/10/2013

81 Increment/Decrement Register This register is used to increment or decrement the value of Stack Pointer. During PUSH operation, the value of Stack Pointer is incremented. During POP operation, the value of Stack Pointer is decremented. Faculty of Computer Application,Gharaun Campus,Mohali 8111/10/2013

82 Address Latch It is group of 8 buffers. The upper-byte of 16-bit address is stored in this latch. And then it is made available to the peripheral devices. Faculty of Computer Application,Gharaun Campus,Mohali 8211/10/2013

83 Address/Data Latch The lower-byte of address and 8-bit of data are multiplexed. It holds either lower-byte of address or 8-bits of data. This is decided by ALE (Address Latch Enable) signal. If ALE = 1 then – Address/Data Latch contains lower-byte of address. If ALE = 0 then – It contains 8-bit data. Faculty of Computer Application,Gharaun Campus,Mohali 8311/10/2013

84 Serial I/O Controller It is used to convert serial data into parallel and parallel data into serial. Microprocessor works with 8-bit parallel data. Serial I/O devices works with serial transfer of data. Therefore, this unit is the interface between microprocessor and serial I/O devices. Faculty of Computer Application,Gharaun Campus,Mohali 8411/10/2013

85 Interrupt Controller It is used to handle the interrupts. There are 5 interrupt signals in 8085: – TRAP – RST 7.5 – RST 6.5 – RST 5.5 – INTR Faculty of Computer Application,Gharaun Campus,Mohali 8511/10/2013

86 Interrupt Controller Interrupt controller receives these interrupts according to their priority and applies them to the microprocessor. There is one outgoing signal INTA which is called Interrupt Acknowledge. Faculty of Computer Application,Gharaun Campus,Mohali 8611/10/2013

87 Power Supply This unit provides +5V power supply to the microprocessor. The microprocessor needs +5V power supply for its operation. Faculty of Computer Application,Gharaun Campus,Mohali 8711/10/2013

88 How to increase speed of Operation of 8085? The main use is to hold data which is Frequently used. It increases the speed of program execution. The data in Microprocessor can be stored in memory OR GENERAL PURPOSE registers. If the data is present in memory the mpu has to perform an operation of memory read. This data is taken by microprocessor, The required operation is performed and result is stored back to memory. To store result in memory the microprocessor has to perform one more operation of memory WRITE. So there are two operations involved in using memory to hold data. But if data is present in general purpose register there is no operation involved. As the general purpose registers are part of microprocessor architecture, the microprocessor doesnt have to perform any external memory read and write operation. Thus the time required to execute program using general purpose register is very less as compared to program using memory. Faculty of Computer Application,Gharaun Campus,Mohali 8811/10/2013

89 Further Reading of Covered Topic B. Ram Fundamentals of microprocessors and HI microcomputers,Dhanpat RaiPublication. Chapter :- 3 Page no:- 3.1 to 3.5 Faculty of Computer Application,Gharaun Campus,Mohali 8911/10/2013

90 PIN-Diagram of 8085 Introduction to 8085 It was introduced in It is 8-bit microprocessor. Its actual name is 8085 A. It is single NMOS device. It contains 6200 transistors approx. Its dimensions are 164 mm x 222 mm. It is having 40 pins Dual-Inline-Package (DIP). Faculty of Computer Application,Gharaun Campus,Mohali 9011/10/2013

91 Introduction to 8085 It has three advanced versions: 8085 AH 8085 AH AH1 These advanced versions are designed using HMOS technology. Faculty of Computer Application,Gharaun Campus,Mohali 9111/10/2013

92 Introduction to 8085 The advanced versions consume 20% less power supply. The clock frequencies of 8085 are: 8085 A3 MHz 8085 AH3 MHz 8085 AH25 MHz 8085 AH16 MHz Faculty of Computer Application,Gharaun Campus,Mohali 9211/10/2013

93 Introduction to 8085 The signals are in following groups:- Power supply signals Clock signals Reset signals Interrupt signals Address and data bus Status and control signals Serial input/output Signals DMA request signals Faculty of Computer Application,Gharaun Campus,Mohali 9311/10/2013

94 Pin Diagram of 8085 Faculty of Computer Application,Gharaun Campus,Mohali 9411/10/2013

95 X 1 & X 2 Pin 1 and Pin 2 (Input) Faculty of Computer Application,Gharaun Campus,Mohali 95 These are also called Crystal Input Pins. Crystal is used as a clock source 8085 can generate clock signals internally. To generate clock signals internally, 8085 requires external inputs from X 1 and X 2. 11/10/2013

96 Crystal A crystal oscillator is an electronic oscillator circuit that uses the mechanical resonance of a vibrating crystal of piezoelectric material to create an electrical signal with a very precise frequency. This frequency is commonly used to keep track of time (as in quartz wristwatches), to provide a stable clock signal for digital integrated circuits, and to stabilize frequencies for radio transmitters and receivers. The most common type of piezoelectric resonator used is the quartz crystal, so oscillator circuits designed around them became known as "crystal oscillators."electronic oscillatorresonancecrystalpiezoelectric material frequencyquartz wristwatchesclock signaldigitalintegrated circuitsradio transmittersreceiversquartz crystal 11/10/2013 Faculty of Computer Application,Gharaun Campus,Mohali 96

97 X 1 & X 2 Pin 1 and Pin 2 (Input) Intel 8085 needs 3.07 MHz frequency as a clock signal. generally we know that,clock frequency is half of the crystal frequency. so we connect crystal between pin no 1 & 2 in order to make 6.14 MHz frequency accurately. so that we have crystal frequency of 3.07 MHz for Intel 8085 microprocessor. Why crystal is a preferred clock source? Because of high stability, large Q (Quality Factor) & the frequency that doesnt drift with aging. Crystal is used as a clock source most of the times. 11/10/2013 Faculty of Computer Application,Gharaun Campus,Mohali 97

98 RESET IN and RESET OUT Pin 36 (Input) and Pin 3 (Output) Faculty of Computer Application,Gharaun Campus,Mohali 98 RESET IN: It is used to reset the microprocessor. It is active low signal. When the signal on this pin is low for at least 3 clocking cycles, it forces the microprocessor to reset itself. 11/10/2013

99 RESET IN and RESET OUT Pin 36 (Input) and Pin 3 (Output) Faculty of Computer Application,Gharaun Campus,Mohali 99 Resetting the microprocessor means: Clearing the PC and IR. Disabling all interrupts (except TRAP). Disabling the SOD pin. All the buses (data, address, control) are tri- stated. Gives HIGH output to RESET OUT pin. 11/10/2013

100 RESET IN and RESET OUT Pin 36 (Input) and Pin 3 (Output) Faculty of Computer Application,Gharaun Campus,Mohali 100 RESET OUT: It is used to reset the peripheral devices and other ICs on the circuit. It is an output signal. It is an active high signal. The output on this pin goes high whenever RESET IN is given low signal. The output remains high as long as RESET IN is kept low. 11/10/2013

101 SID and SOD Pin 4 (Input) and Pin 5 (Output) Faculty of Computer Application,Gharaun Campus,Mohali 101 SID (Serial Input Data): o It takes 1 bit input from serial port of o Stores the bit at the 8 th position (MSB) of the Accumulator. o RIM (Read Interrupt Mask) instruction is used to transfer the bit. 11/10/2013

102 SID and SOD Pin 4 (Input) and Pin 5 (Output) Faculty of Computer Application,Gharaun Campus,Mohali 102 SOD (Serial Output Data): o It takes 1 bit from Accumulator to serial port of o Takes the bit from the 8 th position (MSB) of the Accumulator. o SIM (Set Interrupt Mask) instruction is used to transfer the bit. 11/10/2013

103 Interrupts 8085 TRAP RST7.5 RST6.5 RST 5.5 INTR INTA Faculty of Computer Application,Gharaun Campus,Mohali 11/10/2013 Faculty of Computer Application,Gharaun Campus,Mohali

104 Interrupt Pins Faculty of Computer Application,Gharaun Campus,Mohali 104 Interrupt: It means interrupting the normal execution of the microprocessor. When microprocessor receives interrupt signal, it discontinues whatever it was executing. It starts executing new program indicated by the interrupt signal. Interrupt signals are generated by external peripheral devices. After execution of the new program, microprocessor goes back to the previous program. 11/10/2013

105 Sequence of Steps Whenever There is an Interrupt Faculty of Computer Application,Gharaun Campus,Mohali 105 Microprocessor completes execution of current instruction of the program. PC contents are stored in stack. PC is loaded with address of the new program. After executing the new program, the microprocessor returns back to the previous program. It goes to the previous program by reading the top value of stack. 11/10/2013

106 Responding to Interrupts Responding to an interrupt may be immediate or delayed depending on whether the interrupt is maskable or non- maskable and whether interrupts are being masked or not. There are two ways of redirecting the execution to the ISR depending on whether the interrupt is vectored or non- vectored. – Vectored: The address of the subroutine is already known to the Microprocessor – Non Vectored: The device will have to supply the address of the subroutine to the Microprocessor Faculty of Computer Application,Gharaun Campus,Mohali 10611/10/2013

107 Five Hardware Interrupts in 8085 Faculty of Computer Application,Gharaun Campus,Mohali 107 TRAP RST 7.5 RST 6.5 RST 5.5 INTR 11/10/2013

108 Classification of Interrupts Faculty of Computer Application,Gharaun Campus,Mohali 108 Maskable and Non-Maskable Vectored and Non-Vectored Edge Triggered and Level Triggered Priority Based Interrupts 11/10/2013

109 MASKING Disabling of interrupt is called MASKING. When interrupt are to be used they are enabled by Software using the instruction ENABLE INTERUPT.[EI].The instruction DISABLE INTERRUPT [DI] is used to disable interupts. Faculty of Computer Application,Gharaun Campus,Mohali 10911/10/2013

110 Maskable Interrupts Faculty of Computer Application,Gharaun Campus,Mohali 110 Maskable interrupts are those interrupts which can be enabled or disabled. Enabling and Disabling is done by software instructions. 11/10/2013

111 Maskable Interrupts Faculty of Computer Application,Gharaun Campus,Mohali 111 List of Maskable Interrupts: RST 7.5 RST 6.5 RST 5.5 INTR 11/10/2013

112 Non-Maskable Interrupts Faculty of Computer Application,Gharaun Campus,Mohali 112 The interrupts which are always in enabled mode are called non-maskable interrupts. These interrupts can never be disabled by any software instruction. TRAP is a non-maskable interrupt. It is not accessible to user. TRAP is usually used for power failure and emergency shutoff. 11/10/2013

113 Vectored Interrupts Faculty of Computer Application,Gharaun Campus,Mohali 113 The interrupts which have fixed memory location for transfer of control from normal execution. Each vectored interrupt points to the particular location in memory. 11/10/2013

114 Vectored Interrupts Faculty of Computer Application,Gharaun Campus,Mohali 114 List of vectored interrupts: RST 7.5 RST 6.5 RST 5.5 TRAP 11/10/2013

115 Vectored Interrupts Faculty of Computer Application,Gharaun Campus,Mohali 115 The addresses to which program control goes: Absolute address is calculated by multiplying the RST value with 0008 H. NameVectored Address RST C H (7.5 x 0008 H) RST H (6.5 x 0008 H) RST C H (5.5 x 0008 H) TRAP0024 H (4.5 x 0008 H) 11/10/2013

116 Non-Vectored Interrupts Faculty of Computer Application,Gharaun Campus,Mohali 116 The interrupts which don't have fixed memory location for transfer of control from normal execution. The address of the memory location is sent along with the interrupt. INTR is a non-vectored interrupt. 11/10/2013

117 Edge Triggered Interrupts Faculty of Computer Application,Gharaun Campus,Mohali 117 The interrupts which are triggered at leading or trailing edge are called edge triggered interrupts. RST 7.5 is an edge triggered interrupt. It is triggered during the leading (positive) edge. 11/10/2013

118 Level Triggered Interrupts Faculty of Computer Application,Gharaun Campus,Mohali 118 The interrupts which are triggered at high or low level are called level triggered interrupts. RST 6.5 RST 5.5 INTR TRAP is edge and level triggered interrupt. 11/10/2013

119 Priority Based Interrupts Faculty of Computer Application,Gharaun Campus,Mohali 119 Whenever there exists a simultaneous request at two or more pins then the pin with higher priority is selected by the microprocessor. Priority is considered only when there are simultaneous requests. 11/10/2013

120 Priority Based Interrupts Faculty of Computer Application,Gharaun Campus,Mohali 120 Priority of interrupts: InterruptPriority TRAP1 RST 7.52 RST 6.53 RST 5.54 INTR5 11/10/2013

121 TRAP Pin 6 (Input) Faculty of Computer Application,Gharaun Campus,Mohali 121 It is an non-maskable interrupt. It has the highest priority. It cannot be disabled. It is both edge and level triggered. It means TRAP signal must go from low to high. And must remain high for a certain period of time. TRAP is usually used for power failure and emergency shutoff. 11/10/2013

122 RST 7.5 Pin 7 (Input) Faculty of Computer Application,Gharaun Campus,Mohali 122 It is a maskable interrupt. It has the second highest priority. It is positive edge triggered only. The internal flip-flop is triggered by the rising edge. The flip-flop remains high until it is cleared by RESET IN. 11/10/2013

123 RST 6.5 Pin 8 (Input) Faculty of Computer Application,Gharaun Campus,Mohali 123 It is a maskable interrupt. It has the third highest priority. It is level triggered only. The pin has to be held high for a specific period of time. RST 6.5 can be enabled by EI instruction. It can be disabled by DI instruction. 11/10/2013

124 RST 5.5 Pin 9 (Input) Faculty of Computer Application,Gharaun Campus,Mohali 124 It is a maskable interrupt. It has the fourth highest priority. It is also level triggered. The pin has to be held high for a specific period of time. This interrupt is very similar to RST /10/2013

125 INTR Pin 10 (Input) Faculty of Computer Application,Gharaun Campus,Mohali 125 It is a maskable interrupt. It has the lowest priority. It is also level triggered. It is a general purpose interrupt. By general purpose we mean that it can be used to vector microprocessor to any specific subroutine having any address. 11/10/2013

126 INTA Pin 11 (Output) Faculty of Computer Application,Gharaun Campus,Mohali 126 It stands for interrupt acknowledge. It is an out going signal. It is an active low signal. Low output on this pin indicates that microprocessor has acknowledged the INTR request. 11/10/2013

127 Address and Data Pins Faculty of Computer Application,Gharaun Campus,Mohali 127 Address Bus: The address bus is used to send address to memory. It selects one of the many locations in memory. Its size is 16-bit. 11/10/2013

128 Address and Data Pins Faculty of Computer Application,Gharaun Campus,Mohali 128 Data Bus: It is used to transfer data between microprocessor and memory. Data bus is of 8-bit. 11/10/2013

129 AD 0 – AD 7 Pin (Bidirectional) Faculty of Computer Application,Gharaun Campus,Mohali 129 These pins serve the dual purpose of transmitting lower order address and data byte. During 1 st clock cycle, these pins act as lower half of address. In remaining clock cycles, these pins act as data bus. The separation of lower order address and data is done by address latch. 11/10/2013

130 A 8 – A 15 Pin (Unidirectional) Faculty of Computer Application,Gharaun Campus,Mohali 130 These pins carry the higher order of address bus. The address is sent from microprocessor to memory. These 8 pins are switched to high impedance state during HOLD and RESET mode. 11/10/2013

131 ALE Pin 30 (Output) Faculty of Computer Application,Gharaun Campus,Mohali 131 It is used to enable Address Latch. It indicates whether bus functions as address bus or data bus. If ALE = 1 then – Bus functions as address bus. If ALE = 0 then – Bus functions as data bus. 11/10/2013

132 S 0 and S 1 Pin 29 (Output) and Pin 33 (Output) Faculty of Computer Application,Gharaun Campus,Mohali 132 S 0 and S 1 are called Status Pins. They tell the current operation which is in progress in S0S0 S1S1 Operation 00Halt 01Write 10Read 11Opcode Fetch 11/10/2013

133 IO/M Pin 34 (Output) Faculty of Computer Application,Gharaun Campus,Mohali 133 This pin tells whether I/O or memory operation is being performed. If IO/M = 1 then – I/O operation is being performed. If IO/M = 0 then – Memory operation is being performed. 11/10/2013

134 IO/M Pin 34 (Output) Faculty of Computer Application,Gharaun Campus,Mohali 134 The operation being performed is indicated by S 0 and S 1. If S 0 = 0 and S 1 = 1 then – It indicates WRITE operation. If IO/M = 0 then – It indicates Memory operation. Combining these two we get Memory Write Operation. 11/10/2013

135 Table Showing IO/M, S 0, S 1 and Corresponding Operations Faculty of Computer Application,Gharaun Campus,Mohali 135 OperationsIO/MS0S0 S1S1 Opcode Fetch011 Memory Read010 Memory Write001 I/O Read110 I/O Write101 Interrupt Ack.111 HaltHigh Impedance00 11/10/2013

136 RD Pin 32 (Output) Faculty of Computer Application,Gharaun Campus,Mohali 136 RD stands for Read. It is an active low signal. It is a control signal used for Read operation either from memory or from Input device. A low signal indicates that data on the data bus must be placed either from selected memory location or from input device. 11/10/2013

137 WR Pin 31 (Output) Faculty of Computer Application,Gharaun Campus,Mohali 137 WR stands for Write. It is also active low signal. It is a control signal used for Write operation either into memory or into output device. A low signal indicates that data on the data bus must be written into selected memory location or into output device. 11/10/2013

138 READY Pin 35 (Input) Faculty of Computer Application,Gharaun Campus,Mohali 138 This pin is used to synchronize slower peripheral devices with fast microprocessor. A low value causes the microprocessor to enter into wait state. The microprocessor remains in wait state until the input at this pin goes high. 11/10/2013

139 HOLD Pin 38 (Input) Faculty of Computer Application,Gharaun Campus,Mohali 139 HOLD pin is used to request the microprocessor for DMA transfer. A high signal on this pin is a request to microprocessor to relinquish the hold on buses. This request is sent by DMA controller. Intel 8257 and Intel 8237 are two DMA controllers. 11/10/2013

140 HLDA Pin 39 (Output) Faculty of Computer Application,Gharaun Campus,Mohali 140 HLDA stands for Hold Acknowledge. The microprocessor uses this pin to acknowledge the receipt of HOLD signal. When HLDA signal goes high, address bus, data bus, RD, WR, IO/M pins are tri-stated. This means they are cut-off from external environment. 11/10/2013

141 HLDA Pin 39 (Output) Faculty of Computer Application,Gharaun Campus,Mohali 141 The control of these buses goes to DMA Controller. Control remains at DMA Controller until HOLD is held high. When HOLD goes low, HLDA also goes low and the microprocessor takes control of the buses. 11/10/2013

142 V SS and V CC Pin 20 (Input) and Pin 40 (Input) Faculty of Computer Application,Gharaun Campus,Mohali V power supply is connected to V CC. Ground signal is connected to V SS. 11/10/2013

143 8085 Interrupts 5 interrupt pins Maskable – INTR – RST5.5, RST6.5, RST7.5 Non-Maskable – TRAP: cannot be disabled by instruction. TRAP has highest priority Once a interrupt is serviced all interrupts except TRAP is disabled Faculty of Computer Application,Gharaun Campus,Mohali 14311/10/2013

144 8085 Interrupts An interrupt is considered to be an emergency signal that may be serviced. – The Microprocessor may respond to it as soon as possible. What happens when MP is interrupted ? – When the Microprocessor receives an interrupt signal, it suspends the currently executing program and jumps to an Interrupt Service Routine (ISR) to respond to the incoming interrupt. – Each interrupt will most probably have its own ISR. Faculty of Computer Application,Gharaun Campus,Mohali 14411/10/2013

145 Interrupts Interrupt is a process where an external device can get the attention of the microprocessor. – The process starts from the I/O device – The process is asynchronous. Classification of Interrupts – Interrupts can be classified into two types: Maskable Interrupts (Can be delayed or Rejected) Non-Maskable Interrupts (Can not be delayed or Rejected) Interrupts can also be classified into: Vectored (the address of the service routine is hard-wired) Non-vectored (the address of the service routine needs to be supplied externally by the device) Faculty of Computer Application,Gharaun Campus,Mohali 14511/10/2013

146 8085 Interrupts When a device interrupts, it actually wants the MP to give a service which is equivalent to asking the MP to call a subroutine. This subroutine is called ISR (Interrupt Service Routine) The EI instruction is a one byte instruction and is used to Enable the non-maskable interrupts. The DI instruction is a one byte instruction and is used to Disable the non-maskable interrupts. The 8085 has a single Non-Maskable interrupt. – The non-maskable interrupt is not affected by the value of the Interrupt Enable flip flop. Faculty of Computer Application,Gharaun Campus,Mohali 14611/10/2013

147 147 The 8085 Interrupts Interrupt nameMaskableVectored INTRYesNo RST 5.5Yes RST 6.5Yes RST 7.5Yes TRAPNoYes

148 TRAP TRAP is the only non-maskable interrupt. – It does not need to be enabled because it cannot be disabled. It has the highest priority amongst interrupts. It is edge and level sensitive. – It needs to be high and stay high to be recognized. – Once it is recognized, it wont be recognized again until it goes low, then high again. TRAP is usually used for power failure and emergency shutoff. Faculty of Computer Application,Gharaun Campus,Mohali 14811/10/2013

149 Further Reading of Covered Topic B. Ram Fundamentals of microprocessors and HI microcomputers,Dhanpat RaiPublication. Chapter :- 3 Page no:- 3.5 to 3.7 Faculty of Computer Application,Gharaun Campus,Mohali 14911/10/2013

150 8085 Machine cycles The 8085 executes several types of instructions with each requiring a different number of operations of different types. However, the operations can be grouped into a small set. The three main types are: Memory Read and Write. I/O Read and Write. Request Acknowledge. Faculty of Computer Application,Gharaun Campus,Mohali 15011/10/2013

151 Opcode Fetch Machine Cycle 1.Step 1 (State T1): In the state,8085 sends the status signals,IO/M,S1 and S0.IO/M=0,S0=1 and S1=1. The 8085 sends a 16- bit address on A8-A15 and AD0-AD7. Faculty of Computer Application,Gharaun Campus,Mohali 15111/10/2013

152 Opcode Fetch Machine Cycle The high order byte of program counter is placed on the A8-A15 lines and it remains there upto T3 state. The lower order byte of program counter is placed on the AD0-AD7 lines which remain there only for T7. Faculty of Computer Application,Gharaun Campus,Mohali 15211/10/2013

153 Opcode Fetch Machine Cycle During this state,ALE gives a positive pulse which represent the content of AD0-AD7 as an address. The ALE signal is used to latch the address to A0-A7. NO control signal is generated in this sate. Faculty of Computer Application,Gharaun Campus,Mohali 15311/10/2013

154 Opcode Fetch Machine Cycle Step 2(State T2): The contents of PC(Lower address bus) will disappear on AD0-AD7 lines, so that the lines can be used as data lines. The contents if A0 – A7 are still available for memory from external latch. Faculty of Computer Application,Gharaun Campus,Mohali 15411/10/2013

155 Opcode Fetch Machine Cycle The control signal RD is made LOW by the processor which enables the read circuit of addressed memory device. The memory device then sends the contents on the data bus i.e. AD0-AD7. In addition to these operations the MP increments PC by 1. Faculty of Computer Application,Gharaun Campus,Mohali 15511/10/2013

156 Opcode Fetch Machine Cycle Step 3:- (State T3) : During this clock cycle, the data from memory i.e. OPCODE is transferred to instruction register and RD control signal is made HIGH. Thus RD disables the memory device. Faculty of Computer Application,Gharaun Campus,Mohali 15611/10/2013

157 Opcode Fetch Machine Cycle Step 4: (State T4): The microprocessor performs only internal operation. The OPCODE is decoded by the CPU and upon decoding 8085 knows all the information about: (i) Whether it should enter T5 and T6 states. (ii) How many bytes of instruction it is? If the instruction does not require T5 and T6 states, it will start or go to next machine cycle. Faculty of Computer Application,Gharaun Campus,Mohali 15711/10/2013

158 Timing diagram. of Memory cycle CLK A 15 -A 8 AD 7 -AD 0 IO/M RD MEMRD A 7 -A 0 Data from MPU Data from memory WR MEMWR T1T1 T2T2 T3T3 ALE T1T1 T2T2 T3T3 READ Cycle WRITE Cycle 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

159 READ Cycle Step 1(State T1):- In T1 state,8085 sends appropriate status signals,IO/M,S0 and S1. IO/M=0,S=0,S1=1(memory read).The 16-bit address is transferred on AD0-AD7. The address is dependant on the operation. In operand fetch cycle, address is given by PC and PC is incremented by 1.In memory read cycle, address depends upon instruction:- Address may be from SP or any General purpose Reg.Pair. ALE is generated by 8085 to indicate the availability of address A0-A7 on AD0-AD7.The ALE is used o latch A0-A7. Faculty of Computer Application,Gharaun Campus,Mohali 15911/10/2013

160 READ Cycle Step -2 (State T2):- In T2 state, the lines ADO-AD7 will be used as D0-D7 to transfer data. The control signal RD is made LOW which will enable the selected memory. The memory will send data on the data bus. Faculty of Computer Application,Gharaun Campus,Mohali 16011/10/2013

161 READ Cycle Step -3 (State T3) :- In T3 State, data from memory is transferred to accepts this data and transfers control on internal data bus and RD is made HIGH. Now where the data is transferred depends on the instruction for which this machine cycle is used. it is generally stored in general purpose register. Faculty of Computer Application,Gharaun Campus,Mohali 16111/10/2013

162 WRITE Cycle Step1(T1) :- In T1 state,8085 sends the appropriate status signals IO/M,S0 and S1.i.e IO/M=0,SO=1,S1=0(memory write).the 16 bit address is transferred on A8-A15 and AD0- AD7.ALE is active for short Duration. Faculty of Computer Application,Gharaun Campus,Mohali 16211/10/2013

163 WRITE Cycle Step 2(T2) :- In T2 state the address on AD0- AD7 i.e. A0-A7 is removed and data to be stored in memory is transferred on these lines. The control signals WR is made LOW will make memory Active to accept the contents of data bus. The accepted contents are stored at selected location. Faculty of Computer Application,Gharaun Campus,Mohali 16311/10/2013

164 WRITE Cycle Step3 (State T3):- In this state, data from data bus is stored at memory location.WR is made HIGH which deactivates memory and microprocessor completes the machine cycle. Faculty of Computer Application,Gharaun Campus,Mohali 16411/10/2013

165 Further Reading of Covered Topic B. Ram Fundamentals of microprocessors and HI microcomputers,Dhanpat Rai Publication. Chapter :- 3 Page no: to 3.14 Faculty of Computer Application,Gharaun Campus,Mohali 16511/10/2013

166 ADDRESSING MODES OF 8085 Faculty of Computer Application,Gharaun Campus,Mohali 16611/10/2013

167 ADDRESSING MODES OF 8085 To perform any operation, we have to give the corresponding instructions to the microprocessor. In each instruction, programmer has to specify 3 things: Operation to be performed. Address of source of data. Address of destination of result. Faculty of Computer Application,Gharaun Campus,Mohali 16711/10/2013

168 ADDRESSING MODES OF 8085 The method by which the address of source of data or the address of destination of result is given in the instruction is called Addressing Modes. The term addressing mode refers to the way in which the operand of the instruction is specified. Faculty of Computer Application,Gharaun Campus,Mohali 16811/10/2013

169 ADDRESSING MODES OF 8085 Types of Addressing Modes Intel 8085 uses the following addressing modes: 1.Direct Addressing Mode 2.Register Addressing Mode 3.Register Indirect Addressing Mode 4.Immediate Addressing Mode 5.Implicit Addressing Mode Faculty of Computer Application,Gharaun Campus,Mohali 16911/10/2013

170 ADDRESSING MODES OF Direct Addressing Mode In this mode, the address of the operand is given in the instruction itself. LDA is the operation H is the address of source. Accumulator is the destination. Faculty of Computer Application,Gharaun Campus,Mohali 170 LDA 2500 HLoad the contents of memory location 2500 H in accumulator. 11/10/2013

171 ADDRESSING MODES OF Register Addressing Mode In this mode, the operand is in general purpose register. MOV is the operation. B is the source of data. A is the destination. Faculty of Computer Application,Gharaun Campus,Mohali 171 MOV A, BMove the contents of register B to A. 11/10/2013

172 ADDRESSING MODES OF Register Indirect Addressing Mode In this mode, the address of operand is specified by a register pair. MOV is the operation. M is the memory location specified by H-L register pair. A is the destination. Faculty of Computer Application,Gharaun Campus,Mohali 172 MOV A, MMove data from memory location specified by H-L pair to accumulator. 11/10/2013

173 ADDRESSING MODES OF Immediate Addressing Mode In this mode, the operand is specified within the instruction itself. MVI is the operation. 05 H is the immediate data (source). A is the destination. Faculty of Computer Application,Gharaun Campus,Mohali 173 MVI A, 05 HMove 05 H in accumulator. 11/10/2013

174 ADDRESSING MODES OF Implicit Addressing Mode If address of source of data as well as address of destination of result is fixed, then there is no need to give any operand along with the instruction. CMA is the operation. A is the source. A is the destination. Faculty of Computer Application,Gharaun Campus,Mohali 174 CMAComplement accumulator. 11/10/2013

175 ADDRESSING MODES OF 8085 Further Reading:- Chapter 4,B.RAM Topic no. 4.3 to Faculty of Computer Application,Gharaun Campus,Mohali 17511/10/2013

176 INSTRUCTIONS SET OF 8085 Faculty of Computer Application,Gharaun Campus,Mohali 17611/10/2013

177 INSTRUCTIONS FOR 8085 The instructions are generally classified into the functional categories as follows:- Data transfer group Arithmetic group Logical group Branching group Stack and Machine control group Faculty of Computer Application,Gharaun Campus,Mohali 17711/10/2013

178 Data Transfer Group Data transfer group of instructions copies data from source to destination without modifying the contents of source. The various types of data transfer that are possible between registers and memory locations as follows:- Faculty of Computer Application,Gharaun Campus,Mohali 17811/10/2013

179 Data Transfer Group S.NOData TransferExample 1.Between RegistersReg B Reg D 2.Specific data byte to register or a memory Location Data Byte Reg B 3. Between Memory Location and RegisterMem.Loc. Reg A 4.Between an I/O device and accumulatorInput Device Reg. A 5.Between a Reg. Pair and the StackReg. Pair data Stack Location Faculty of Computer Application,Gharaun Campus,Mohali 17911/10/2013

180 Data Transfer Group The Data Transfer group of instruction include the Following Instructions:- Faculty of Computer Application,Gharaun Campus,Mohali MOV Rd,Rs9.LHLD address 2.MOV R,M10.SHLD address 3.MOV M,R11.LDAX Rp 4.MVI R,Data12.STAX Rp 5.MVI M,Data13. XCHG 6.LXI Rp,16-bit Data 7.LDA address 8.STA address 11/10/2013

181 Data Transfer Group 1. MOV Rd,Rs Faculty of Computer Application,Gharaun Campus,Mohali 181 MnemonicMOV Rd,Rs OperationRd=Rs No.of Bytes1 byte Machine Cycle1 (OF) FlagsNo flags are Modified AlgorithmRd Rs Addr.ModeRegister addressing Mode T-States4 11/10/2013

182 Data Transfer Group Description:- This instruction copies data from source register Rs to destination Register Rd. The source register Rs and destination register Rd can be any general purpose register like A,B,C,D,E,H or L. The contents of Source register remain unchanged. Faculty of Computer Application,Gharaun Campus,Mohali 18211/10/2013

183 Data Transfer Group Example:- MOV B,C This instruction will copy the contents of register C to register B. The contents of Register C remain unchanged. Suppose B=20H,C=10H and Instruction MOV B,C is executed. After the execution B=10H and C=10H. Faculty of Computer Application,Gharaun Campus,Mohali 18311/10/2013

184 Data Transfer Group 2. MOV R,M Faculty of Computer Application,Gharaun Campus,Mohali 184 MNEMONICMOV R,M OperationR=M or R=(HL) No.of Bytes1 byte Machine Cycle2(OF+MR) FlagsNO flags are modified AlgorithmR M or R (HL) Addressing Mode Indirect Addressing Mode T-states4+3=7 11/10/2013

185 Data Transfer Group Description:- This instruction Copies data from memory M to register R. The term M specifies the HL memory Pointer. The content of HL register pair are used as the address of Memory Location. The contents of that Memory location are transferred to the specified register R. The register R can be any General purpose register. Faculty of Computer Application,Gharaun Campus,Mohali 18511/10/2013

186 Data Transfer Group Example:- MOV C,M This instruction will copy the data from the memory location pointed by HL register pair to C register. Let the contents of HL register pair be 2000H,reg C=20H.At the address 2000H:10H is stored. The HL register pair contents are used as address.i.e HL=2000H. The contents of memory location 2000H are copied to C register, So Contents of Reg.C, Will change from 20H to 10H. The contents of Memory location remain unchanged. Faculty of Computer Application,Gharaun Campus,Mohali 18611/10/2013

187 Data Transfer Group 3. MOV M,R Faculty of Computer Application,Gharaun Campus,Mohali 187 MNEMONICMOV M,R OperationM=R or (HL)=R No. of Bytes1 byte Machine cycles2(OF+ MW) FlagsNO Flags are modified AlgorithmM R or (HL) R Addressing ModeIndirect addressing Mode T-states4+3=7 11/10/2013

188 Data Transfer Group Description This instruction will copy the data from the register to memory M. The HL register pair is used as the memory pointer. The contents of the specified register are copied o that memory location pointed by HL Reg. Pair. The specified register may be any general purpose reg.A,B,C,D,E,H or L. The contents of the specified register remains unchanged. Faculty of Computer Application,Gharaun Campus,Mohali 18811/10/2013

189 Data Transfer Group EXAMPLE:-MOV M,C Let the content of HL pair are 2050H. Reg C=05H, at the address 2050H=25h is stored. On the instruction MOV M,C the data is transferred from C to 2050H. The contents of the Reg C are copied to memory location 2050H,So contents of Memory location 2050H will change from 25H to 05H. Faculty of Computer Application,Gharaun Campus,Mohali 18911/10/2013

190 Data Transfer Group 4. MVI R,Data Faculty of Computer Application,Gharaun Campus,Mohali 190 MNEMONICMVI R,DATA OPERATIONR=DATA No.of bytes2 bytes Machine cycle2(OF+MR) FlagsNo flags are Affected AlgorithmR Data Addressing ModeImmediate addressing Mode T-states7(4+3) 11/10/2013

191 Data Transfer Group Description:- This instruction moves the 8 bit immediate data to the specified register. The data is specified within the instruction. It is a 2-byte instruction, so FIRST byte of instruction will be OPCODE and second byte will be 8-bit data. The Reg. R may be any General purpose register like A,B,C,D,E,H or L. Faculty of Computer Application,Gharaun Campus,Mohali 19111/10/2013

192 Data Transfer Group EXAMPLE:- MVI D,07 This instruction will load the immediate data 07H in Reg.D. Let the contents of Reg D =10H.Then after execution of instruction MVI D,O7H, the contents of D will change from 10H to 07H. Faculty of Computer Application,Gharaun Campus,Mohali 19211/10/2013

193 Data Transfer Group 5. MVI M,Data Faculty of Computer Application,Gharaun Campus,Mohali 193 MNEMONICMVI M,DATA OPERATIONM=DATA or (HL)=DATA NO.OF BYTES2 BYTES MACHINE CYCLES3(OF+MR+MW) FlagsNo Flags are affected AlgorithmM data or (HL) data Addressing ModeImmediate/Indirect addressing Mode T-States10(4+3+3) 11/10/2013

194 Data Transfer Group Description:- This instruction moves immediate data to memory. The HL register Pair is used as memory Pointer. The contents of HL Reg. Pair are used as memory address and immediate data is transferred to that memory location. Faculty of Computer Application,Gharaun Campus,Mohali 19411/10/2013

195 Data Transfer Group Example:- MVI H,10H MVI L, 00H MVI M,20H When the instruction MVI M,2OH is executed the data 20H will be stored in the memory location addressed by HL pair register.ie 1000H. Faculty of Computer Application,Gharaun Campus,Mohali 19511/10/2013

196 Data Transfer Group 6. LXI Rp,16-bit data Faculty of Computer Application,Gharaun Campus,Mohali 196 MnemonicLXI Rp,16 bit data OperationRp=16 bit data No.of bytes3 bytes Machine Cycle3(OF+MR+MW) FLAGSNO flags are affected AlgorithmRp 16 bit data Addressing ModeImmediate Addressing Mode T-states10(4+3+3) 11/10/2013

197 Data Transfer Group Description:- This instruction will load register pair with 16-bit data. This instruction loads 16-bit data specified within the instruction to the specified register pair or stack pointer. In the instruction only high order register is specified for register pair.ie if HL only H register will be specified. The register pair Rp can be BC,DE,HL or Stack pointer SP. Faculty of Computer Application,Gharaun Campus,Mohali 19711/10/2013

198 Data Transfer Group Example:- (i)LXI H,2030H Load HL pair with 2030H.i.e 20H will be loaded in register H and 30H will be loaded in reg L. (ii) LXI SP,2000H Load SP with 2000H. Faculty of Computer Application,Gharaun Campus,Mohali 19811/10/2013

199 Data Transfer Group 7.LDA Address Faculty of Computer Application,Gharaun Campus,Mohali 199 MNEMONICLDA Address OperationA=(address) No. of Bytes3 bytes Machine Cycles4 (OF+MR+MR+MR) FlagsNo flags are effected AlgorithmA (address) Addressing modeDirect addressing mode T-states13( ) 11/10/2013

200 Data Transfer Group Description:- Load accumulator direct from Memory This instruction copies the contents of the memory location whose address is specified in the instruction to the accumulator. The contents of the memory location remain unchanged. Faculty of Computer Application,Gharaun Campus,Mohali 20011/10/2013

201 Data Transfer Group Example:- LDA 3000H This instruction will load the accumulator with the contents of memory location 3000H. Let initially A=F0H,Contents of memory location 3000H=15H. Then after the execution of instruction LDA 3000H,the accumulator will be loaded with 15H.the contents of accumulator will change form F0 to 15H. Faculty of Computer Application,Gharaun Campus,Mohali 20111/10/2013

202 Data Transfer Group 8.STA Address Faculty of Computer Application,Gharaun Campus,Mohali 202 MNEMONICSTA address OPERATION(address)=A NO of Bytes3 bytes Machine Cycles4(OF+MR+MR+MW) FlagsNo flags are effected Algorithm(Address) A Addressing ModeDirect Addressing Mode T-states13( ) 11/10/2013

203 Data Transfer Group Description:- Store accumulator direct to memory. This instruction will store the contents of the accumulator to the memory location specified in the instruction. The contents of memory location remain unchanged. It is 3 byte instruction. The first byte is the opcode,second byte is Lower order address and third byte is higher order address. Faculty of Computer Application,Gharaun Campus,Mohali 20311/10/2013

204 Data Transfer Group Example:- STA 2050H This instruction will store contents of accumulator at memory location 2050H. Faculty of Computer Application,Gharaun Campus,Mohali 20411/10/2013

205 Data Transfer Group 9. LHLD Address Faculty of Computer Application,Gharaun Campus,Mohali 205 MnemonicLHLD Address OperationL= (address) H=(address+1) No. of bytes3 bytes Machine cycles5(OF+MR+MR+MR+MR) FlagsNo flags are effected AlgorithmL (address) H (address+1) Addressing modeDirect addressing mode T-states16( ) 11/10/2013

206 Data Transfer Group Description:- Load HL pair directly from memory This instruction loads the contents of the memory location to the H and L registers. The address of memory is specified along with the instruction. The contents of memory location whose address is specified in the instruction are transferred to L register and the contents of the next memory location i.e.(address+1) to the H register. It is 3 byte instruction. The first byte is the opcode,second byte is the lower order address and third byte is the higher order address. Faculty of Computer Application,Gharaun Campus,Mohali 20611/10/2013

207 Data Transfer Group Example:- LHLD 2000H Load HL pair from memory location 2000H and 2001H. Let H=05H,L=04H at memory location 2000H and 2001H the data 20H and 30H is stored. The instruction LHLD will load the contents of memory location 2000H to L reg. and contents of 2001H to H reg. So the contents of register L will change from 04 to 20H and contents of register H will change from 05H to 30H. Faculty of Computer Application,Gharaun Campus,Mohali 20711/10/2013

208 Data Transfer Group 10. SHLD Address Faculty of Computer Application,Gharaun Campus,Mohali 208 MnemonicSHLD Address Operation(Address)=L register (Address+1)= H register No. of bytes3 bytes Machine cycle5(OF+MR+MR+MW+MW) FlagsNo flags are effected Algorithm(address) L (address+1) H Addressing ModeDirect addressing Mode T-states16( ) 11/10/2013

209 Data Transfer Group Description:- STORE HL PAIR DIRECT IN MEMORY 1.This instruction copies the contents of registers H and L to the memory locations. 2.The address of memory location is specified along with the instruction. 3.The contents of L register are stored at the memory location whose address is specified and the contents of the H register to the (address+1) location. 4.It is a three byte instruction. The first byte is the opcode,second byte is the lower order address and third byte is the higher order address. Faculty of Computer Application,Gharaun Campus,Mohali 20911/10/2013

210 Data Transfer Group Example:- SHLD 3000H 1.Store HL pair to memory location 3000 and Let H=05,L=06,at memory locations 3000 and 3001 is stored and instruction SHLD 3000H is executed,the contents register L is copied to 3000H and contents of H register is copied to 3001H. Faculty of Computer Application,Gharaun Campus,Mohali 21011/10/2013

211 Data Transfer Group 11. LDAX Rp Faculty of Computer Application,Gharaun Campus,Mohali 211 MnemonicLDAX Rp OperationA=(Rp) No. Of bytes1 byte Machine cycles2(OF+MR) FlagsNo flags are effected AlgorithmA (Rp) Addressing ModeIndirect addressing Mode T-States7(4+3) 11/10/2013

212 Data Transfer Group Description:- Load accumulator indirect by using a memory pointer. 1.This instruction copies the content of the memory location to the accumulator. 2.The address of memory location is given by Rp register pair specified along with the instruction. 3.The contents of the memory location remain unchanged. Faculty of Computer Application,Gharaun Campus,Mohali 21211/10/2013

213 Data Transfer Group Example:- LDAX B 1.This instruction will load accumulator with the contents of memory location whose address is given by the BC register. 2.Let A=1FH, B=20H,C=25H.at memory location 2025=56H is stored. 3.Then after execution of instruction LDAX B,the accumulator will be loaded with the contents of memory location 2025 i.e. 56H. Faculty of Computer Application,Gharaun Campus,Mohali 21311/10/2013

214 Data Transfer Group 12. STAX Rp. Faculty of Computer Application,Gharaun Campus,Mohali 214 MnemonicSTAX Rp Operation(Rp)=A No. of bytes1 byte Machine cycles2(OF+MW) FlagsNo flags are effected Algorithm(Rp) A Addressing ModeIndirect addressing Mode T-states7(4+3) 11/10/2013

215 Data Transfer Group Description:- Store accumulator indirect by using a memory pointer 1.This instruction copies the contents of accumulator to memory location. 2.The address of memory location is given by Rp register pair specified along with the instruction. 3.The contents of the accumulator remain unchanged. Faculty of Computer Application,Gharaun Campus,Mohali 21511/10/2013

216 Data Transfer Group Example:- STAX D 1.This instruction will store contents of accumulator to the memory location whose address is given by the DE register Pair. 2.Let A= 1FH,D= 26H,E=08H,at memory location 2608:10 is stored. 3.Then after execution of STAX D instruction, the memory location 2608 will contain IFH. Faculty of Computer Application,Gharaun Campus,Mohali 21611/10/2013

217 Data Transfer Group 13. XCHG Faculty of Computer Application,Gharaun Campus,Mohali 217 Mnemonic XCHG OperationH D L E No. of bytes1 byte Machine Cycles1(OF) No. of FlagsNo flags are effected AlgorithmH D L E Addressing ModeRegister Addressing Mode T-states4 11/10/2013

218 Data Transfer Group Description:- Exchange the contents of HL with DE pair 1.This instruction exchanges the content of H register with D register and L register with E register. Example:- XCHG 1. Let H =12H,L=11H,D=30H,E=40H, and the instruction XCHG is executed. Faculty of Computer Application,Gharaun Campus,Mohali 21811/10/2013

219 Arithmetic Instructions These instructions perform the operations like: Addition Subtraction Increment Decrement Faculty of Computer Application,Gharaun Campus,Mohali 21911/10/2013

220 Arithmetic Instructions Addition Any 8-bit number, or the contents of register, or the contents of memory location can be added to the contents of accumulator. The result (sum) is stored in the accumulator. No two other 8-bit registers can be added directly. Example: The contents of register B cannot be added directly to the contents of register C. Faculty of Computer Application,Gharaun Campus,Mohali 22011/10/2013

221 Arithmetic Instructions Addition Any 8-bit number, or the contents of register, or the contents of memory location can be added to the contents of accumulator. The result (sum) is stored in the accumulator. No two other 8-bit registers can be added directly. Example: The contents of register B cannot be added directly to the contents of register C. Faculty of Computer Application,Gharaun Campus,Mohali 22111/10/2013

222 Arithmetic Instructions Subtraction Any 8-bit number, or the contents of register, or the contents of memory location can be subtracted from the contents of accumulator. The result is stored in the accumulator. Subtraction is performed in 2s complement form. If the result is negative, it is stored in 2s complement form. No two other 8-bit registers can be subtracted directly. Faculty of Computer Application,Gharaun Campus,Mohali 22211/10/2013

223 Increment / Decrement The 8-bit contents of a register or a memory location can be incremented or decremented by 1. The 16-bit contents of a register pair can be incremented or decremented by 1. Increment or decrement can be performed on any register or a memory location. Faculty of Computer Application,Gharaun Campus,Mohali 22311/10/2013

224 Arithmetic Instructions OpcodeOperandDescription ADDRMRM Add register or memory to accumulator Faculty of Computer Application,Gharaun Campus,Mohali 224 The contents of register or memory are added to the contents of accumulator. The result is stored in accumulator. If the operand is memory location, its address is specified by H-L pair. All flags are modified to reflect the result of the addition. Example: ADD B or ADD M 11/10/2013

225 Arithmetic Instructions OpcodeOperandDescription ADCRMRM Add register or memory to accumulator with carry Faculty of Computer Application,Gharaun Campus,Mohali 225 The contents of register or memory and Carry Flag (CY) are added to the contents of accumulator. The result is stored in accumulator. If the operand is memory location, its address is specified by H-L pair. All flags are modified to reflect the result of the addition. Example: ADC B or ADC M 11/10/2013

226 Arithmetic Instructions OpcodeOperandDescription ADI8-bit dataAdd immediate to accumulator The 8-bit data is added to the contents of accumulator. The result is stored in accumulator. All flags are modified to reflect the result of the addition. Example: ADI 45 H 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

227 Arithmetic Instructions OpcodeOperandDescription ACI8-bit dataAdd immediate to accumulator with carry The 8-bit data and the Carry Flag (CY) are added to the contents of accumulator. The result is stored in accumulator. All flags are modified to reflect the result of the addition. Example: ACI 45 H 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

228 Arithmetic Instructions OpcodeOperandDescription DADReg. pairAdd register pair to H-L pair The 16-bit contents of the register pair are added to the contents of H-L pair. The result is stored in H-L pair. If the result is larger than 16 bits, then CY is set. No other flags are changed. Example: DAD B 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

229 Arithmetic Instructions OpcodeOperandDescription SUBRMRM Subtract register or memory from accumulator The contents of the register or memory location are subtracted from the contents of the accumulator. The result is stored in accumulator. If the operand is memory location, its address is specified by H-L pair. All flags are modified to reflect the result of subtraction. Example: SUB B or SUB M 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

230 Arithmetic Instructions OpcodeOperandDescription SBBRMRM Subtract register or memory from accumulator with borrow The contents of the register or memory location and Borrow Flag (i.e. CY) are subtracted from the contents of the accumulator. The result is stored in accumulator. If the operand is memory location, its address is specified by H-L pair. All flags are modified to reflect the result of subtraction. Example: SBB B or SBB M 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

231 Arithmetic Instructions OpcodeOperandDescription SUI8-bit dataSubtract immediate from accumulator The 8-bit data is subtracted from the contents of the accumulator. The result is stored in accumulator. All flags are modified to reflect the result of subtraction. Example: SUI 45 H 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

232 Arithmetic Instructions OpcodeOperandDescription SBI8-bit dataSubtract immediate from accumulator with borrow The 8-bit data and the Borrow Flag (i.e. CY) is subtracted from the contents of the accumulator. The result is stored in accumulator. All flags are modified to reflect the result of subtraction. Example: SBI 45 H 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

233 Arithmetic Instructions OpcodeOperandDescription INRRMRM Increment register or memory by 1 The contents of register or memory location are incremented by 1. The result is stored in the same place. If the operand is a memory location, its address is specified by the contents of H-L pair. Example: INR B or INR M 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

234 Arithmetic Instructions OpcodeOperandDescription INXRIncrement register pair by 1 The contents of register pair are incremented by 1. The result is stored in the same place. Example: INX H 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

235 Arithmetic Instructions OpcodeOperandDescription DCRRMRM Decrement register or memory by 1 The contents of register or memory location are decremented by 1. The result is stored in the same place. If the operand is a memory location, its address is specified by the contents of H-L pair. Example: DCR B or DCR M 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

236 Arithmetic Instructions OpcodeOperandDescription DCXRDecrement register pair by 1 The contents of register pair are decremented by 1. The result is stored in the same place. Example: DCX H 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

237 Logical Instructions These instructions perform logical operations on data stored in registers, memory and status flags. The logical operations are: AND OR XOR Rotate Compare Complement 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

238 AND, OR, XOR Any 8-bit data, or the contents of register, or memory location can logically have AND operation OR operation XOR operation with the contents of accumulator. The result is stored in accumulator. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

239 Rotate Each bit in the accumulator can be shifted either left or right to the next position. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

240 Compare Any 8-bit data, or the contents of register, or memory location can be compares for: Equality Greater Than Less Than with the contents of accumulator. The result is reflected in status flags. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

241 Complement The contents of accumulator can be complemented. Each 0 is replaced by 1 and each 1 is replaced by 0. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

242 Logical Instructions OpcodeOperandDescription CMPRMRM Compare register or memory with accumulator The contents of the operand (register or memory) are compared with the contents of the accumulator. Both contents are preserved. The result of the comparison is shown by setting the flags of the PSW as follows: 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

243 Logical Instructions OpcodeOperandDescription CMPRMRM Compare register or memory with accumulator if (A) < (reg/mem): carry flag is set if (A) = (reg/mem): zero flag is set if (A) > (reg/mem): carry and zero flags are reset. Example: CMP B or CMP M 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

244 Logical Instructions OpcodeOperandDescription CPI8-bit dataCompare immediate with accumulator The 8-bit data is compared with the contents of accumulator. The values being compared remain unchanged. The result of the comparison is shown by setting the flags of the PSW as follows: 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

245 Logical Instructions OpcodeOperandDescription CPI8-bit dataCompare immediate with accumulator if (A) < data: carry flag is set if (A) = data: zero flag is set if (A) > data: carry and zero flags are reset Example: CPI 89H 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

246 Logical Instructions OpcodeOperandDescription ANARMRM Logical AND register or memory with accumulator The contents of the accumulator are logically ANDed with the contents of register or memory. The result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of H-L pair. S, Z, P are modified to reflect the result of the operation. CY is reset and AC is set. Example: ANA B or ANA M. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

247 Logical Instructions OpcodeOperandDescription ANI8-bit dataLogical AND immediate with accumulator The contents of the accumulator are logically ANDed with the 8-bit data. The result is placed in the accumulator. S, Z, P are modified to reflect the result. CY is reset, AC is set. Example: ANI 86H. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

248 Logical Instructions OpcodeOperandDescription XRARMRM Exclusive OR register or memory with accumulator The contents of the accumulator are XORed with the contents of the register or memory. The result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of H-L pair. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. Example: XRA B or XRA M. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

249 Logical Instructions OpcodeOperandDescription ORARMRM Logical OR register or memory with accumulator The contents of the accumulator are logically ORed with the contents of the register or memory. The result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of H-L pair. S, Z, P are modified to reflect the result. CY and AC are reset. Example: ORA B or ORA M. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

250 Logical Instructions OpcodeOperandDescription ORI8-bit dataLogical OR immediate with accumulator The contents of the accumulator are logically ORed with the 8- bit data. The result is placed in the accumulator. S, Z, P are modified to reflect the result. CY and AC are reset. Example: ORI 86H. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

251 Logical Instructions OpcodeOperandDescription XRARMRM Logical XOR register or memory with accumulator The contents of the accumulator are XORed with the contents of the register or memory. The result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of H-L pair. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. Example: XRA B or XRA M. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

252 Logical Instructions OpcodeOperandDescription XRI8-bit dataXOR immediate with accumulator The contents of the accumulator are XORed with the 8-bit data. The result is placed in the accumulator. S, Z, P are modified to reflect the result. CY and AC are reset. Example: XRI 86H. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

253 Logical Instructions OpcodeOperandDescription RLCNoneRotate accumulator left Each binary bit of the accumulator is rotated left by one position. Bit D7 is placed in the position of D0 as well as in the Carry flag. CY is modified according to bit D7. S, Z, P, AC are not affected. Example: RLC. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

254 Logical Instructions OpcodeOperandDescription RRCNoneRotate accumulator right Each binary bit of the accumulator is rotated right by one position. Bit D0 is placed in the position of D7 as well as in the Carry flag. CY is modified according to bit D0. S, Z, P, AC are not affected. Example: RRC. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

255 Logical Instructions OpcodeOperandDescription RALNoneRotate accumulator left through carry Each binary bit of the accumulator is rotated left by one position through the Carry flag. Bit D7 is placed in the Carry flag, and the Carry flag is placed in the least significant position D0. CY is modified according to bit D7. S, Z, P, AC are not affected. Example: RAL. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

256 Logical Instructions OpcodeOperandDescription RARNoneRotate accumulator right through carry Each binary bit of the accumulator is rotated right by one position through the Carry flag. Bit D0 is placed in the Carry flag, and the Carry flag is placed in the most significant position D7. CY is modified according to bit D0. S, Z, P, AC are not affected. Example: RAR. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

257 Logical Instructions OpcodeOperandDescription CMANoneComplement accumulator The contents of the accumulator are complemented. No flags are affected. Example: CMA. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

258 Logical Instructions OpcodeOperandDescription CMCNoneComplement carry The Carry flag is complemented. No other flags are affected. Example: CMC. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

259 Logical Instructions OpcodeOperandDescription STCNoneSet carry The Carry flag is set to 1. No other flags are affected. Example: STC. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

260 Branching Instructions The branching instruction alter the normal sequential flow. These instructions alter either unconditionally or conditionally. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

261 Branching Instructions OpcodeOperandDescription JMP16-bit addressJump unconditionally The program sequence is transferred to the memory location specified by the 16-bit address given in the operand. Example: JMP 2034 H. This instruction will load the PC with 2034 H and the processor will fetch the instruction from this address. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali DescriptionThis instruction loads the PC with the address given within the instruction and continues with the program execution from this location

262 Branching Instructions OpcodeOperandDescription Jx16-bit addressJump conditionally The program sequence is transferred to the memory location specified by the 16-bit address given in the operand based on the specified flag of the PSW. Example: JZ 2034 H. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali DescriptionIn condition JUMP instruction,when the condition is true or satisfied then only JUMP is made at the specified address. If condition is false or not satisfied it will just check and proceed further to execute the next instruction after it.

263 Branching Instructions Example: JZ 2034 H. Let Z=0 This instruction will cause a JUMP to an address 2034 H.i.e PC will load with 2034 as ZF=1. 11/10/2013 Faculty of Computer Application,Gharaun Campus,Mohali 263

264 Jump Conditionally OpcodeDescriptionStatus Flags JCJump if CarryCY = 1 JNCJump if No CarryCY = 0 JPJump if PositiveS = 0 JMJump if MinusS = 1 JZJump if ZeroZ = 1 JNZJump if No ZeroZ = 0 JPEJump if Parity EvenP = 1 JPOJump if Parity OddP = 0 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

265 Branching Instructions OpcodeOperandDescription CALL16-bit addressCall unconditionally The program sequence is transferred to the memory location specified by the 16-bit address given in the operand. Before the transfer, the address of the next instruction after CALL (the contents of the program counter) is pushed onto the stack. Example: CALL 2034 H. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

266 Branching Instructions OpcodeOperandDescription Cx16-bit addressCall conditionally The program sequence is transferred to the memory location specified by the 16-bit address given in the operand based on the specified flag of the PSW. Before the transfer, the address of the next instruction after the call (the contents of the program counter) is pushed onto the stack. Example: CZ 2034 H. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

267 Call Conditionally OpcodeDescriptionStatus Flags CCCall if CarryCY = 1 CNCCall if No CarryCY = 0 CPCall if PositiveS = 0 CMCall if MinusS = 1 CZCall if ZeroZ = 1 CNZCall if No ZeroZ = 0 CPECall if Parity EvenP = 1 CPOCall if Parity OddP = 0 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

268 Branching Instructions OpcodeOperandDescription RETNoneReturn unconditionally The program sequence is transferred from the subroutine to the calling program. The two bytes from the top of the stack are copied into the program counter, and program execution begins at the new address. Example: RET. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

269 Branching Instructions OpcodeOperandDescription RxNoneCall conditionally The program sequence is transferred from the subroutine to the calling program based on the specified flag of the PSW. The two bytes from the top of the stack are copied into the program counter, and program execution begins at the new address. Example: RZ. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

270 Return Conditionally OpcodeDescriptionStatus Flags RCReturn if CarryCY = 1 RNCReturn if No CarryCY = 0 RPReturn if PositiveS = 0 RMReturn if MinusS = 1 RZReturn if ZeroZ = 1 RNZReturn if No ZeroZ = 0 RPEReturn if Parity EvenP = 1 RPOReturn if Parity OddP = 0 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

271 Branching Instructions OpcodeOperandDescription RST0 – 7Restart (Software Interrupts) The RST instruction jumps the control to one of eight memory locations depending upon the number. These are used as software instructions in a program to transfer program execution to one of the eight locations. Example: RST 3. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

272 Restart Address Table InstructionsRestart Address RST H RST H RST H RST H RST H RST H RST H RST H 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

273 Control Instructions The control instructions control the operation of microprocessor. 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

274 Control Instructions OpcodeOperandDescription NOPNoneNo operation No operation is performed. The instruction is fetched and decoded but no operation is executed. Example: NOP 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

275 Control Instructions OpcodeOperandDescription HLTNoneHalt The CPU finishes executing the current instruction and halts any further execution. An interrupt or reset is necessary to exit from the halt state. Example: HLT 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

276 Control Instructions OpcodeOperandDescription DINoneDisable interrupt The interrupt enable flip-flop is reset and all the interrupts except the TRAP are disabled. No flags are affected. Example: DI 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

277 Control Instructions OpcodeOperandDescription EINoneEnable interrupt The interrupt enable flip-flop is set and all interrupts are enabled. No flags are affected. This instruction is necessary to re-enable the interrupts (except TRAP). Example: EI 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

278 Control Instructions OpcodeOperandDescription RIMNoneRead Interrupt Mask This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 and read serial data input bit. The instruction loads eight bits in the accumulator with the following interpretations. Example: RIM 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

279 RIM Instruction 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

280 Control Instructions OpcodeOperandDescription SIMNoneSet Interrupt Mask This is a multipurpose instruction and used to implement the 8085 interrupts 7.5, 6.5, 5.5, and serial data output. The instruction interprets the accumulator contents as follows. Example: SIM 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali

281 SIM Instruction 11/10/ Faculty of Computer Application,Gharaun Campus,Mohali


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