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Dennis Byrne Memory Barriers.

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Presentation on theme: "Dennis Byrne Memory Barriers."— Presentation transcript:

1 Dennis Byrne dennisbyrne@apache.org Memory Barriers

2 Defining the Problem Object connection = null; boolean initialized = false; // thread 1 writestwice // thread 2 reads twice connection = new Connection(); if(initialized) initialized = true; connection.use(); NullPointerException ?

3 Root Cause: Memory Latency Processors work hard to avoid memory latency – memory operations (reads & writes) are re-ordered This is not a problem when … – data is local and/or immutable – there is only single processor People do this also …

4 Introduction Memory barriers, or fences, are a set of processor instructions used to apply ordering limitations on read and write operations.

5 Visibility is kind of important – The Java Memory Model – Erlang send operators – Retlang and Jetlang Channels – C++ atomics – Scala Actors – Every semaphore, mutex, or atomic operation

6 Classifying Memory Barriers Which memory operations does this membar sit between? – LoadLoad – LoadWrite – WriteWrite – WriteLoad Which memory operations are we serializing? – Unidirectional – Bidirectional

7 Dekkers Algorithm // 1st thread intentFirst = true; while (intentSecond) if (turn != 0) { intentFirst = false; while (turn != 0) {} intentFirst = true; } criticalSection(); turn = 1; intentFirst = false; // 2nd thread intentSecond = true; while (intentFirst) if (turn != 1) { intentSecond = false; while (turn != 1) {} intentSecond = true; } criticalSection(); turn = 0; intentSecond = false;

8 Consecutive Volatile Writes on Itanium 2 1 adds r37=592,r36;; ;...0b284149 0421 2st4.rel [r37]=r39 ;...00389560 2380 3adds r36=596,r36;; ;...84112544 4 st1.rel [r36]=r0 ;...09000048 a011 5 mf ;...00000044 0000 6 nop.i 0x0;; ;...00040000 7 mov r12=r33 ;...00600042 0021 8 mov.ret b0=r35,0x2000000001de81e0 The other side of the protocol ….

9 Consecutive Volatile Reads on Itanium 2 1 adds r37=597,r36;; ;...84112554 2 ld1.acq r38=[r37];; ;...0b30014a a010 3 nop.m 0x0 ;...00000002 00c0 4 sxt1 r38=r38;; ;...00513004 5 cmp4.eq p0,p6=0,r38 ;...1100004c 8639 6 nop.i 0x0 ;...00000002 0003 7 br.cond.dpnt.many 0x2000000001de8220;; One side of the protocol ….

10 Implicit Memory Barriers mov 0x160(%edi),%edi ;...8bbf6001 0000 mov %ecx,%edi ;...8bf9 add $0x8,%edi ;...83c708 lock cmpxchg %esi,(%edi) ;...f00fb137 mov $0x1,%eax ;...b8010000 00 Atomic CAS operation on x86 lock cmpxchg serializes pending memory operations

11 Avoiding Memory Barriers Atomic CAS on a VMWare image with one processor: add $0x8,%edi ;...83c708 cmpxchg %esi,(%edi) ;...0fb137 mov $0x1,%eax ;...b8010000 00 Consecutive volatile reads in Java on SPARC: ld [ %l1 + 0x150 ], %i0 ;...f0046150 sethi %hi(0xff3fc000), %l0 ;...213fcff0 ld [ %l0 ], %g0 ;...c0042000 ret ;...81c7e008

12 Memory Barriers Thanks Dennis Byrne – DRW Trading dennisbyrne@apache.org


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