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DSP C5000 Chapter 9 Understanding and Programming the Multi-channel Buffered Serial Port (McBSP) Copyright © 2003 Texas Instruments. All rights reserved.

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Presentation on theme: "DSP C5000 Chapter 9 Understanding and Programming the Multi-channel Buffered Serial Port (McBSP) Copyright © 2003 Texas Instruments. All rights reserved."— Presentation transcript:

1 DSP C5000 Chapter 9 Understanding and Programming the Multi-channel Buffered Serial Port (McBSP) Copyright © 2003 Texas Instruments. All rights reserved.

2 ESIEE, Slide 2Outline Application of McBSP Application of McBSP on McBSP on C5416 and C5510 C5416 and C5510 Differences between C5416 and C5510 Differences between C5416 and C5510 References Configuration with CSL Configuration with CSL

3 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 3 Application of McBSP McBSP = Multichannel Buffered Serial Port McBSP = Multichannel Buffered Serial Port Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected A/D - D/A and serial devices. Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected A/D - D/A and serial devices. Direct connection to other C5000 devices, Direct connection to other C5000 devices, Usually works in connection with DMA Usually works in connection with DMA

4 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 4 Audio System using DMA and McBSP Lets take a closer look at how the buffers are organized...

5 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 5 Ping-Pong Buffers In order to make the application less real-time critical, the input is double buffered In order to make the application less real-time critical, the input is double buffered These buffers are called ping-pong buffers These buffers are called ping-pong buffers The configuration is that of a two frame circular buffer The configuration is that of a two frame circular buffer First fill one buffer, then fill the other, then switch back to the first First fill one buffer, then fill the other, then switch back to the first What about the output buffers?

6 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 6 The Flow 1 of 4 What needs to happen to the DMA Channels?

7 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 7 The Flow 2 of 4 What buffers can the application use to process?

8 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 8 The Flow 3 of 4 How do we know when new buffers are ready?

9 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 9 The Flow 4 of 4 And everything starts over…on to the hardware!!

10 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 10 McBSP on C5416 and C5510 C5416 and C5510 McBSP are very similar C5416 and C5510 McBSP are very similar The small differences will be discussed in a later section The small differences will be discussed in a later section 3 McBSPs on C5416 and C McBSPs on C5416 and C5510 Basic pins on serial ports (R for Read and X for Transmit): Basic pins on serial ports (R for Read and X for Transmit): BDR or BDX: serial data BDR or BDX: serial data BCLKR or BCLKX: clock at bit rate BCLKR or BCLKX: clock at bit rate BFSR or BFSX: frame synchronization (word rate) BFSR or BFSX: frame synchronization (word rate)

11 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 11 Multi-Channel Buffered Serial Port (McBSP) Full duplex, max bit rate = ½ CPU clock Full duplex, max bit rate = ½ CPU clock Word length: 8, 12, 16,20, 24, 32 Word length: 8, 12, 16,20, 24, 32 Frame length (between FS): words Frame length (between FS): words

12 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 12 McBSP Interface Signals

13 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 13 More Features of the McBSP 1 of 2 Double-buffered transmission and triple-buffered reception Double-buffered transmission and triple-buffered reception Independent clocking and framing for transmit and receive. Independent clocking and framing for transmit and receive. Capability to send interrupts to the CPU and DMA event to the DMA controller. Capability to send interrupts to the CPU and DMA event to the DMA controller. External shift clock generation or an internal programmable-frequency clock External shift clock generation or an internal programmable-frequency clock Highly programmable internal clock and frame generation Highly programmable internal clock and frame generation Programmable sample rate generator Programmable sample rate generator 128 channels. 128 channels.

14 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 14 More Features of the McBSP 2 of 2 Programmable polarity for both frame synchronization and data clocks Programmable polarity for both frame synchronization and data clocks 8-bit data transfers with option of LSB or MSB first 8-bit data transfers with option of LSB or MSB first -Law and A-Law companding -Law and A-Law companding

15 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 15 Bit Ordering Normally, transfers using the McBSP are sent and received with the MSB first. Normally, transfers using the McBSP are sent and received with the MSB first. Certain 8-bit data protocols (that do not use companded data) require the LSB to be transferred first: Certain 8-bit data protocols (that do not use companded data) require the LSB to be transferred first: By setting (R/X)COMPAND = 01b in (R/X)CR2, the bit ordering of 8-bit words is reversed (LSB first). By setting (R/X)COMPAND = 01b in (R/X)CR2, the bit ordering of 8-bit words is reversed (LSB first). This feature is only enabled if the appropriate (R/X)WDLEN[1,2] is set to 0, (8-bit words). This feature is only enabled if the appropriate (R/X)WDLEN[1,2] is set to 0, (8-bit words). If either phase of the frame does not have an 8-bit word length, the McBSP assumes the word length is 8 bits, and LSB-first ordering is done. If either phase of the frame does not have an 8-bit word length, the McBSP assumes the word length is 8 bits, and LSB-first ordering is done.

16 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 16 McBSP Data and Control Paths The letter B before the pin names is omitted on this figure, ie DX instead of BDX. It will also be the case in the following slides.

17 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 17 McBSP Control Registers for Clock and Frame Synchronisation and Control The x at the end of a register name represents the number of the McBSP device: McBSP 0,1 or 2.

18 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 18 McBSP Control Registers for Channel Selection 8 partitions A, B, C, D, E, F, G, H 8 partitions A, B, C, D, E, F, G, H The x at the end of a register name represents the number of the McBSP device: McBSP 0,1 or 2.

19 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 19 McBSP Configuration Via SPCR1, SPCR2 and PCR registers Via SPCR1, SPCR2 and PCR registers These contain status information and bits that can be configured for the required operation. These contain status information and bits that can be configured for the required operation. PCR PCR Configures the McBSP pins as inputs or outputs during normal serial port operation, Configures the McBSP pins as inputs or outputs during normal serial port operation, Configures the pins as general purpose inputs or outputs during receiver and/or transmitter reset. Configures the pins as general purpose inputs or outputs during receiver and/or transmitter reset.

20 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 20 Configuration of McBSP, SPCR1 Register DLB= Digital Loop Back Mode DLB= Digital Loop Back Mode RJUST = Receive Sign-Extension and Justification Mode RJUST = Receive Sign-Extension and Justification Mode CLKSTP = Clock Stop Mode CLKSTP = Clock Stop Mode DXENA = DX delay Enabler DXENA = DX delay Enabler ABIS = A-bis mode ABIS = A-bis mode RINTM = Receive Interrupt Mode RINTM = Receive Interrupt Mode RSYNCERR = Receive Synchronization Error RSYNCERR = Receive Synchronization Error RFULL = Receiver shift Register full RFULL = Receiver shift Register full RRDY = Receiver Ready RRDY = Receiver Ready RRST = Receiver Reset RRST = Receiver Reset

21 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 21 Configuration of McBSP, SPCR2 Register FREE = Free Running mode (in emulation) FREE = Free Running mode (in emulation) SOFT = Soft bit (in emulation) SOFT = Soft bit (in emulation) FRST = Frame-sync generator Reset FRST = Frame-sync generator Reset GRST = Sample rate generator Reset GRST = Sample rate generator Reset

22 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 22 Configuration of McBSP PCR Pin Control Register XIOEN = Transmit general purpose IO mode XIOEN = Transmit general purpose IO mode RIOEN = Receive general purpose IO mode RIOEN = Receive general purpose IO mode FSXM = Transmit Frame-Synchronization Mode FSXM = Transmit Frame-Synchronization Mode FSRM = Receive Frame-Synchronization Mode FSRM = Receive Frame-Synchronization Mode CLKXM, CLKRM = Transmitter (Receiver) clock Mode CLKXM, CLKRM = Transmitter (Receiver) clock Mode CLKS_STAT = Status of CLKS pin when GPIO CLKS_STAT = Status of CLKS pin when GPIO DX_STAT, DR_STAT = Status of DX (DR) when GPIO DX_STAT, DR_STAT = Status of DX (DR) when GPIO FSXP, FSRP = Transmit (receive) Frame-Sync. Polarity FSXP, FSRP = Transmit (receive) Frame-Sync. Polarity CLKXP, CLKRP = Transmit (receive) Clock Polarity CLKXP, CLKRP = Transmit (receive) Clock Polarity

23 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 23 Receive and Transmit Control Registers RCR and XCR RCR1 RFLEN1 = Receive Frame Length 1 (1 to 128 words / frame) RFLEN1 = Receive Frame Length 1 (1 to 128 words / frame) RWDLEN1 = Receive Word Length 1 (8, 12, 16, 20, 24, 32 bits) RWDLEN1 = Receive Word Length 1 (8, 12, 16, 20, 24, 32 bits) RCR2 RPHASE = Receive phases (single or dual frames) RPHASE = Receive phases (single or dual frames) RFLEN2 =Receive Frame Length 2 (1 to 128 words / frame) RFLEN2 =Receive Frame Length 2 (1 to 128 words / frame) RWDLEN2 = Receive Word Length 2 (8, 12, 16, 20, 24, 32 bits) RWDLEN2 = Receive Word Length 2 (8, 12, 16, 20, 24, 32 bits) RCOMPAND = Receive companding mode RCOMPAND = Receive companding mode RFIG = Receive Frame Ignore RFIG = Receive Frame Ignore RDATDLY =Receive Data Delay RDATDLY =Receive Data Delay Structure of XCR1 and XCR2 is similar to that of RCR1 and RCR2.

24 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 24 McBSP Reset (R/X)RST and RESET (R/X)RST and RESET Device reset (RS = 0) places the receiver, transmitter and the sample rate generator SRGR in reset. Device reset (RS = 0) places the receiver, transmitter and the sample rate generator SRGR in reset. When the device reset is removed (RS = 1) GRST = FRST = RRST = XRST = 0, keeping the entire serial port in the reset state. When the device reset is removed (RS = 1) GRST = FRST = RRST = XRST = 0, keeping the entire serial port in the reset state. The SP transmitter and receiver can be independently reset by the RRST and XRST bits in the SPCR registers. The SRGR is reset by the GRST bit in SPCR2. The SP transmitter and receiver can be independently reset by the RRST and XRST bits in the SPCR registers. The SRGR is reset by the GRST bit in SPCR2.

25 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 25 Determining Ready Status RRDY and XRDY indicate the ready state of the McBSP receiver and transmitter. RRDY and XRDY indicate the ready state of the McBSP receiver and transmitter. Serial port writes and reads may be synchronized: Serial port writes and reads may be synchronized: By polling RRDY and XRDY, By polling RRDY and XRDY, or by using the events to DMA or by using the events to DMA REVT and XEVT in normal mode, REVT and XEVT in normal mode, and REVTA and XEVTA in A-bis mode, and REVTA and XEVTA in A-bis mode, or by interrupts to CPU (RINT and XINT), which the events generate. or by interrupts to CPU (RINT and XINT), which the events generate. Note that reading DRR[1,2] and writing to DXR[1,2] affect RRDY and XRDY. Note that reading DRR[1,2] and writing to DXR[1,2] affect RRDY and XRDY.

26 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 26 Frame and Clock Configuration The McBSP allows independent configurations of data clock and frame synchronization for receive and transmit: The McBSP allows independent configurations of data clock and frame synchronization for receive and transmit: Polarities of FSR, FSX, CLKX, and CLKR Polarities of FSR, FSX, CLKX, and CLKR A choice of single- or dual-phase frames A choice of single- or dual-phase frames For each phase, the number of words per frame For each phase, the number of words per frame For each phase, the number of bits per word For each phase, the number of bits per word Subsequent frame synchronization may restart the serial data stream or be ignored. Subsequent frame synchronization may restart the serial data stream or be ignored. The data bit delay from frame synchronization to first data bit can be 0-, The data bit delay from frame synchronization to first data bit can be 0-, 1-, or 2-bit delays. 1-, or 2-bit delays. Right- or left-justification as well as sign-extension or zero-filling can be chosen for receive data. Right- or left-justification as well as sign-extension or zero-filling can be chosen for receive data.

27 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 27 Frame and Clock Operation Receive and transmit frame-sync pulses can be generated: Receive and transmit frame-sync pulses can be generated: Either internally by the sample rate generator SRGR, Either internally by the sample rate generator SRGR, or driven by an external source. or driven by an external source. The source of frame sync is selected by the mode bit, FS(R/X)M, in the PCR. The source of frame sync is selected by the mode bit, FS(R/X)M, in the PCR. FSR is affected by GSYNC bit in SRGR2 FSR is affected by GSYNC bit in SRGR2 Receive and transmit clocks can be selected to be inputs or outputs by the mode bit, CLK(R/X)M, in the PCR. Receive and transmit clocks can be selected to be inputs or outputs by the mode bit, CLK(R/X)M, in the PCR.

28 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 28 Sample Rate Generator

29 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 29 Sample Rate Generator Register SRGR SRGR 1 FWID = Frame Width FWID = Frame Width CLKGDV = Sample rate generator Clock Divider CLKGDV = Sample rate generator Clock Divider SRGR 2 GSYNC = SRGR Clock synchronization GSYNC = SRGR Clock synchronization CLKSP = Polarity Clock edge selection CLKSP = Polarity Clock edge selection CLKSM = SRGR Clock Mode CLKSM = SRGR Clock Mode FSGM = SRGR transmit Frame-Sync Mode FSGM = SRGR transmit Frame-Sync Mode FPER = Frame Period FPER = Frame Period

30 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 30 Data Clock Generation When (CLK[R/X]M = 1), the data clocks (CLK[R/X]) are driven by: When (CLK[R/X]M = 1), the data clocks (CLK[R/X]) are driven by: the internal SRGR output clock, CLKG. the internal SRGR output clock, CLKG. The input clock to the SRGR can be either the CPU clock or a dedicated external clock input (CLKS). The input clock to the SRGR can be either the CPU clock or a dedicated external clock input (CLKS). The CLKSM bit in SRGR2 selects either the CPU clock (CLKSM = 1) or the external clock input (CLKSM = 0) CLKS. The CLKSM bit in SRGR2 selects either the CPU clock (CLKSM = 1) or the external clock input (CLKSM = 0) CLKS. The input clock source to the SRGR can be divided down by a programmable value (CLKGDV) to drive CLKG The input clock source to the SRGR can be divided down by a programmable value (CLKGDV) to drive CLKG Regardless of the source to the SRGR, the rising edge of CLKSRG generates CLKG and FSG Regardless of the source to the SRGR, the rising edge of CLKSRG generates CLKG and FSG

31 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 31 Digital Loop Back Mode DLB DLB = 1 in SPCR1 enables digital loop back mode. DLB = 1 in SPCR1 enables digital loop back mode. During DLB mode, DR, FSR, and CLKR are internally connected through multiplexers to DX, FSX, CLKX, respectively. During DLB mode, DR, FSR, and CLKR are internally connected through multiplexers to DX, FSX, CLKX, respectively. DLB mode allows testing of serial port code with a single DSP device. DLB mode allows testing of serial port code with a single DSP device. In digital loop back mode, the transmitter clock drives the receiver. CLKRM determines whether the CLKR pin is an input or an output. In digital loop back mode, the transmitter clock drives the receiver. CLKRM determines whether the CLKR pin is an input or an output.

32 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 32 Frame-sync Signal Generation When FRST=1 in SPCR2, it activates the frame-sync generation logic to generate a frame-sync signal, if FSGM = 1 in SRGR2. When FRST=1 in SPCR2, it activates the frame-sync generation logic to generate a frame-sync signal, if FSGM = 1 in SRGR2. Frame-sync programming options: Frame-sync programming options: A frame pulse with a programmable period and programmable active width, using the SRGR1 register, A frame pulse with a programmable period and programmable active width, using the SRGR1 register, The transmit portion may trigger its own frame-sync signal generated by a DXR[1,2]-to-XSR[1,2] copy, The transmit portion may trigger its own frame-sync signal generated by a DXR[1,2]-to-XSR[1,2] copy, Both the receive and transmit sections may independently select an external frame synchronization on the FSR and FSX pins, respectively. Both the receive and transmit sections may independently select an external frame synchronization on the FSR and FSX pins, respectively.

33 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 33 McBSP - Example Problem: transfer bit words to SARAM, extl CLK/FS, no CPU int Problem: transfer bit words to SARAM, extl CLK/FS, no CPU int - Bit/CLKR shifted into RSR - RSR RBR - RBR DRR (RRDY=1) - REVT sync event activates DMA (no McBSP setup) - DMA transfers DRR to SARAM …repeat Operation

34 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 34 Multichannel Selection Operation A McBSP channel is a time slot for shifting in/out the bits of one serial word. A McBSP channel is a time slot for shifting in/out the bits of one serial word. Each McBSP supports up to 128 channels. Each McBSP supports up to 128 channels. The 128 channels are divided into 8 blocks of 16 consecutive channels: The 128 channels are divided into 8 blocks of 16 consecutive channels: Block 0: Channels 0-15 Block 0: Channels 0-15 Block 1: Channels … Block 1: Channels … Block 7: Channels Block 7: Channels The blocks are assigned to partitions: The blocks are assigned to partitions: In C5410 or C5420, only 2 partitions A or B In C5410 or C5420, only 2 partitions A or B In the C5416 and C5510, choice between 2 partitions (A,B) or 8 partitions (A, B, C, …H.) In the C5416 and C5510, choice between 2 partitions (A,B) or 8 partitions (A, B, C, …H.)

35 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 35 Multichannel Partition Mode In the 2 partitions mode: In the 2 partitions mode: One even-numbered block (0,2,4,6) is assigned to partition A and one odd- numbered block (1,3,5,7) to partition B. One even-numbered block (0,2,4,6) is assigned to partition A and one odd- numbered block (1,3,5,7) to partition B. Up to 32 channels can be selected. Up to 32 channels can be selected. In the 8 partitions mode, blocks 0 through 7 are automatically assigned to partitions A through H. In the 8 partitions mode, blocks 0 through 7 are automatically assigned to partitions A through H. Up to 128 channels can be selected. Up to 128 channels can be selected. The number of partitions for reception and transmission are independent. The number of partitions for reception and transmission are independent.

36 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 36 Multichannel Selection When a McBSP uses a TDM (Time Division Multiplex) data stream, it may need to select only a few channels to save memory and bandwidth. When a McBSP uses a TDM (Time Division Multiplex) data stream, it may need to select only a few channels to save memory and bandwidth. Each channel partition has a dedicated channel enable register. Each channel partition has a dedicated channel enable register. If the multichannel selection mode is on, each bit in the register controls whether a channel is selected or not in the partition. If the multichannel selection mode is on, each bit in the register controls whether a channel is selected or not in the partition. There is 1 receive multichannel selection mode and 3 transmit modes. There is 1 receive multichannel selection mode and 3 transmit modes.

37 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 37 Configuring a Frame for Multichannel Selection Select a single-phase frame: Select a single-phase frame: RPHASE/WPHASE = 0 RPHASE/WPHASE = 0 Each frame represents a TDM data stream. Each frame represents a TDM data stream. Set a frame length (R/X)FRLEN1 including the highest-numbered channel in the selection. Set a frame length (R/X)FRLEN1 including the highest-numbered channel in the selection.

38 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 38 Control of Multichannel Selection The multichannel mode can be enabled independently for receive and transmit by setting RMCM = 1 and XMCM to a non-zero value in control registers MCR[1,2], respectively. The multichannel mode can be enabled independently for receive and transmit by setting RMCM = 1 and XMCM to a non-zero value in control registers MCR[1,2], respectively. Choose the partition mode: 2 or 8 partitions, with the RMCME and/or XMCME bits: Choose the partition mode: 2 or 8 partitions, with the RMCME and/or XMCME bits: (R/X)MCME = 0, 2 partitions A-B (R/X)MCME = 0, 2 partitions A-B (R/X)MCME = 1, 8 partitions A-B…H (R/X)MCME = 1, 8 partitions A-B…H

39 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 39 Multichannel Operation Control Registers MCR1, MCR2: Multichannel control registers MCR1, MCR2: Multichannel control registers XCERx: transmit channel enable registers XCERx: transmit channel enable registers x = a letter A, B, C, D, E, F or H x = a letter A, B, C, D, E, F or H RCERx: receive channel enable registers RCERx: receive channel enable registers x = a letter A, B, C, D, E, F or H x = a letter A, B, C, D, E, F or H

40 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 40 Multichannel Operation MCR1 Register MCR1 for C5410 or C5420 RPBBLK = Receive Partition B Block RPBBLK = Receive Partition B Block RPABLK = Receive Partition A Block RPABLK = Receive Partition A Block RCBLK = Receive Current Block RCBLK = Receive Current Block RMCM = Receive Multichannel Selection Enable RMCM = Receive Multichannel Selection Enable MCR1 for C5416 and C5510 RMCME = Receive Multichannel Partition Mode bit, applicable if channel can be individually selected RMCM = 1 RMCME = Receive Multichannel Partition Mode bit, applicable if channel can be individually selected RMCM = 1

41 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 41 Multichannel Operation MCR2 Register MCR 2 for C5410 or C54 20 MCR 2 for C5416 and C5510 MCR2 has the same structure as MCR1 but for transmission. MCR2 has the same structure as MCR1 but for transmission. The XMCM bits of XCR2 determine whether all channels or only selected channels are enabled and unmasked for transmission. The XMCM bits of XCR2 determine whether all channels or only selected channels are enabled and unmasked for transmission. There are 3 transmit multichannel selection modes There are 3 transmit multichannel selection modes 00b: No selection. All channels are enabled and unmasked. 00b: No selection. All channels are enabled and unmasked. 01b: All channels are disabled unless selected in XCERs registers. If enabled, a channel is also unmasked. 01b: All channels are disabled unless selected in XCERs registers. If enabled, a channel is also unmasked. 10b: All channels are enabled, but they are masked unless they are selected in XCERs registers. 10b: All channels are enabled, but they are masked unless they are selected in XCERs registers. 11 b: symmetric transmission/reception. All channels are disabled for transmission unless they are enabled for reception in RCER registers. Once enabled, they are masked unless they are also selected in the XCERs registers. 11 b: symmetric transmission/reception. All channels are disabled for transmission unless they are enabled for reception in RCER registers. Once enabled, they are masked unless they are also selected in the XCERs registers.

42 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 42 Using 2 partitions A and B McBSP channels are activated using an alternating scheme. After a sync pulse: McBSP channels are activated using an alternating scheme. After a sync pulse: Receiver or transmitter begins with the channels in partition A and alternates between part. B and A until the end of the frame. Receiver or transmitter begins with the channels in partition A and alternates between part. B and A until the end of the frame. Assigning blocks to partitions. Any 2 of the 8 blocks can be assigned to A and B: Assigning blocks to partitions. Any 2 of the 8 blocks can be assigned to A and B: Assign an even-numbered block to A by writing the 2 (R/X)PABLK bits and an odd-numbered block to B (R/X)PBBLK. Assign an even-numbered block to A by writing the 2 (R/X)PABLK bits and an odd-numbered block to B (R/X)PBBLK. The channels are controlled the receive or transmit channel enable registers (R/X)CERCA, (R/X)CERA. The channels are controlled the receive or transmit channel enable registers (R/X)CERCA, (R/X)CERA.

43 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 43 Using 2 partitions A and B Blocks can be reassigned during communication if we want to use more than 32 selected channels. Blocks can be reassigned during communication if we want to use more than 32 selected channels. It is not possible to modify the block assignment of a partition during its transfer. It is not possible to modify the block assignment of a partition during its transfer. The block currently involved in the transmission is reflected in the (R/X)CBLK bits. They can be polled. The block currently involved in the transmission is reflected in the (R/X)CBLK bits. They can be polled. At the end of a block, an interrupt can be sent to the CPU that checks (R/X)CBLK bits and updates the inactive partition. At the end of a block, an interrupt can be sent to the CPU that checks (R/X)CBLK bits and updates the inactive partition.

44 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 44 Using 8 Partitions RMCME/XMCME = 1 RMCME/XMCME = 1 Partitions are activated in the order: Partitions are activated in the order: A B C D E F G H. A B C D E F G H. The (R/X)PABLK and (R/X)PBBLK are ignored. The (R/X)PABLK and (R/X)PBBLK are ignored. The blocks are assigned to the partitions in natural order: The blocks are assigned to the partitions in natural order: A: block 0, channels 0 to 15, reg. (R/X)CERA A: block 0, channels 0 to 15, reg. (R/X)CERA B: block 1, channels 16 to 31, reg. (R/X)CERB B: block 1, channels 16 to 31, reg. (R/X)CERB … H: block 7, chan. 112 to 127, reg. (R/X)CERH H: block 7, chan. 112 to 127, reg. (R/X)CERH

45 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 45 Receive Channels Disabled If a receive channel is disabled, any bits received in that channel are passed only as far as the receive buffer register(s) (RBR(s)). If a receive channel is disabled, any bits received in that channel are passed only as far as the receive buffer register(s) (RBR(s)). The receiver does not copy the content of the RBR(s) to the DRR(s), and as a result, does not set the receiver ready bit (RRDY). The receiver does not copy the content of the RBR(s) to the DRR(s), and as a result, does not set the receiver ready bit (RRDY). Therefore, no DMA synchronization event (REVT) is generated, and if the receiver interrupt mode depends on RRDY (RINTM = 00b), no interrupt is generated. Therefore, no DMA synchronization event (REVT) is generated, and if the receiver interrupt mode depends on RRDY (RINTM = 00b), no interrupt is generated.

46 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 46 Enabling/Disabling versus Masking/Unmasking For transmission, a channel may be: For transmission, a channel may be: Enabled and unmasked Enabled and unmasked Transmission can begin and be completed Transmission can begin and be completed Enabled: Data are passed from DXR to XSR. Enabled: Data are passed from DXR to XSR. Unmasked: Data in XSR shifted out on DX pin. Unmasked: Data in XSR shifted out on DX pin. Enabled and masked Enabled and masked Transmission can begin but cannot be completed Transmission can begin but cannot be completed Masked: DX pin is held in high impedance. Avoids bus contention on a shared serial bus. Masked: DX pin is held in high impedance. Avoids bus contention on a shared serial bus. Disabled Disabled Transmission cannot occur. No DXR to XSR copy. Transmission cannot occur. No DXR to XSR copy. The bit XRDY is not set. The bit XRDY is not set.

47 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 47 Channel Enable Registers RCERx and XCERx RCERARCERARCERARCERA XCERAXCERAXCERAXCERA In C5410 and C5420, there are 2 receive and 2 transmit Channel Enable Registers: RCERA, RCERB, XCERA, XCERB. In C5410 and C5420, there are 2 receive and 2 transmit Channel Enable Registers: RCERA, RCERB, XCERA, XCERB. In C5416 and C5510, there are 8 receive + 8 transmit Channel Enable Registers: RCERA to RCERH and XCERA to XCERH. In C5416 and C5510, there are 8 receive + 8 transmit Channel Enable Registers: RCERA to RCERH and XCERA to XCERH.

48 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 48 SPI Mode The SPI protocol is a master-slave configuration, with one master device and one or more slave devices. The interface consists of four signals. The SPI protocol is a master-slave configuration, with one master device and one or more slave devices. The interface consists of four signals. The clock stop mode of the McBSP provides compatibility with the SPI protocol. The clock stop mode of the McBSP provides compatibility with the SPI protocol.

49 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 49 McBSP Pins as General Purpose I/O pins 1 of 2 Two conditions allow the serial port pins (CLKX, FSX, DX, CLKR, FSR and DR) to be used as general purpose input/output (I/O) rather than serial port pins: Two conditions allow the serial port pins (CLKX, FSX, DX, CLKR, FSR and DR) to be used as general purpose input/output (I/O) rather than serial port pins: 1) The related portion (transmitter or receiver) of the serial port is in reset; (R/X)RST = 0 in SPCR[1,2]. 1) The related portion (transmitter or receiver) of the serial port is in reset; (R/X)RST = 0 in SPCR[1,2]. 2) General purpose I/O is enabled for the related portion of the serial port; (R/X)IOEN = 1 in the PCR. 2) General purpose I/O is enabled for the related portion of the serial port; (R/X)IOEN = 1 in the PCR. In the case of FS(R/X), FS(R/X)M=0(or 1) configures the pin as an input (or output). In the case of FS(R/X), FS(R/X)M=0(or 1) configures the pin as an input (or output). When configured as an output, the value driven on FS(R/X) is the value stored in FS(R/X)P. When configured as an output, the value driven on FS(R/X) is the value stored in FS(R/X)P. If configured as an input, FS(R/X)P becomes a read-only bit that reflects the status of that signal. If configured as an input, FS(R/X)P becomes a read-only bit that reflects the status of that signal.

50 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 50 McBSP Pins as General Purpose I/O pins 2 of 2 CLK(R/X)M and CLK(R/X)P work similarly for CLK(R/X). CLK(R/X)M and CLK(R/X)P work similarly for CLK(R/X). DX and DR as GPIO pins: DX and DR as GPIO pins: the value of the DX_STAT bit in the PCR is driven onto DX. the value of the DX_STAT bit in the PCR is driven onto DX. DR is always an input and its value is held in the DR_STAT bit in the PCR. DR is always an input and its value is held in the DR_STAT bit in the PCR. CLKS as a general purpose input: CLKS as a general purpose input: both the transmitter and receiver must be in reset state and (R/X)IOEN = 1, because CLKS is always an input to the McBSP and affects both transmit and receive operations. both the transmitter and receiver must be in reset state and (R/X)IOEN = 1, because CLKS is always an input to the McBSP and affects both transmit and receive operations.

51 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 51 McBSP Operation in Power-down Mode For the C5416, Power-down modes may be invoked in several ways: For the C5416, Power-down modes may be invoked in several ways: executing the IDLE instruction or driving the HOLD input low with the HM status bit set to one. executing the IDLE instruction or driving the HOLD input low with the HM status bit set to one. The McBSP can take the CPU out of IDLE using a transmit or receive interrupt. The McBSP can take the CPU out of IDLE using a transmit or receive interrupt. When in IDLE1 or HOLD modes, the McBSP continues to operate normally with no restrictions. When in IDLE1 or HOLD modes, the McBSP continues to operate normally with no restrictions. In IDLE2 or IDLE3 modes, the internal device clocks provided to the peripherals are stopped. In IDLE2 or IDLE3 modes, the internal device clocks provided to the peripherals are stopped. If external clock and frame-sync are provided, the McBSP can continue to operate, and receive and transmit interrupts can be used to exit the IDLE state. If external clock and frame-sync are provided, the McBSP can continue to operate, and receive and transmit interrupts can be used to exit the IDLE state. If either clocks or frame-syncs are internal, the McBSP will stop in IDLE2/3. If either clocks or frame-syncs are internal, the McBSP will stop in IDLE2/3. In IDLE2/3, the internal clocks to the McBSP and the DMA controller are started automatically when a transfer begins, and stopped after the transferis completed. In IDLE2/3, the internal clocks to the McBSP and the DMA controller are started automatically when a transfer begins, and stopped after the transferis completed.

52 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 52 McBSP Operation in Power-down Mode For the C5510,The McBSP is placed into its idle mode when: For the C5510, The McBSP is placed into its idle mode when: the PERIPH idle domain is idle (PERIS = 1 in ISTR) the PERIPH idle domain is idle (PERIS = 1 in ISTR) the McBSP idle enable bit is set (SPn = 1) in the PICR register. When the McBSP is in the Idle state, it is unable to receive or transmit data. the McBSP idle enable bit is set (SPn = 1) in the PICR register. When the McBSP is in the Idle state, it is unable to receive or transmit data. In the McBSP idle mode: In the McBSP idle mode: If the McBSP is operates with internal clocking and frame sync., it will be completely stopped. If the McBSP is operates with internal clocking and frame sync., it will be completely stopped. If the McBSP is operates with ext. clocking and frame sync., the external interface portion of the McBSP continues to function during external clock activity periods. The McBSP sends a request to activate the PERIPH and DMA idle domains when it needs to be serviced. If the domains were idle, they are made idle again after the McBSP has been serviced. If the McBSP is operates with ext. clocking and frame sync., the external interface portion of the McBSP continues to function during external clock activity periods. The McBSP sends a request to activate the PERIPH and DMA idle domains when it needs to be serviced. If the domains were idle, they are made idle again after the McBSP has been serviced.

53 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 53 Emulation FREE and SOFT Bits FREE and SOFT are special emulation bits that determine the state of the serial port clock when a breakpoint is encountered in the high-level language debugger. FREE and SOFT are special emulation bits that determine the state of the serial port clock when a breakpoint is encountered in the high-level language debugger. If the FREE bit is set to 1 If the FREE bit is set to 1 upon a software breakpoint, the clock continues to run (free runs) and data still shifts out. When FREE = 1, the SOFT bit is a dont care. upon a software breakpoint, the clock continues to run (free runs) and data still shifts out. When FREE = 1, the SOFT bit is a dont care. If the FREE bit is cleared to zero, then the SOFT bit takes effect. If the FREE bit is cleared to zero, then the SOFT bit takes effect. If the SOFT bit is cleared to zero, then the clock stops immediately, thus aborting a transmission. If the SOFT bit is cleared to zero, then the clock stops immediately, thus aborting a transmission. If the SOFT bit is set to one and a transmission is in progress, the transmission continues until completion of the transfer, and then the clock halts. If the SOFT bit is set to one and a transmission is in progress, the transmission continues until completion of the transfer, and then the clock halts. The receiver-side functions in a similar fashion. The receiver-side functions in a similar fashion.

54 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 54 Differences Between C5416 and C5510 McBSP Addressing of McBSP registers: Addressing of McBSP registers: C5416: sub-bank system C5416: sub-bank system Some registers are mapped in data memory page 0: DRR, DXR + SPSA and SPSD Some registers are mapped in data memory page 0: DRR, DXR + SPSA and SPSD SPSAx: McBSP Sub-Address register associated with a SPSD Sub-bank Data register containing the value for one of the sub-bank registers SPSAx: McBSP Sub-Address register associated with a SPSD Sub-bank Data register containing the value for one of the sub-bank registers The other registers are sub-bank registers accessed by sub-addresses relative to SPSA. The other registers are sub-bank registers accessed by sub-addresses relative to SPSA. C5510: Registers are mapped in the I/O space C5510: Registers are mapped in the I/O space Power-down modes Power-down modes C5416 McBSP Registers addr.

55 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 55 Configuration of the McBSP 1 of 3 Receiver/transmitter configuration Receiver/transmitter configuration Place the McBSP receiver / transmitter in reset Place the McBSP receiver / transmitter in reset Program the McBSP registers for the desired receiver / transmitter operation Program the McBSP registers for the desired receiver / transmitter operation Take the receiver / transmitter out of reset Take the receiver / transmitter out of reset

56 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 56 Configuration of the McBSP 2 of 3 Global behavior Global behavior Set the receiver pins to operate as McBSP pins Set the receiver pins to operate as McBSP pins Enable/disable the digital loopback mode Enable/disable the digital loopback mode Enable/disable the clock stop mode Enable/disable the clock stop mode Enable/disable the receive multichannel selection mode Enable/disable the receive multichannel selection mode Data behavior Data behavior Choose 1 or 2 phases for the receive frame Choose 1 or 2 phases for the receive frame Set the receive word length(s) Set the receive word length(s) Set the receive frame length Set the receive frame length Enable/disable the receive frame-sync ignore function Enable/disable the receive frame-sync ignore function Set the receive companding mode Set the receive companding mode Set the receive data delay Set the receive data delay Set the receive sign-extension and justification mode Set the receive sign-extension and justification mode Set the receive interrupt mode Set the receive interrupt mode

57 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 57 Configuration of the McBSP 3 of 3 Frame-sync behavior Frame-sync behavior Set the receive frame-sync mode Set the receive frame-sync mode Set the receive frame-sync polarity Set the receive frame-sync polarity Set the SRG frame-sync period and pulse width Set the SRG frame-sync period and pulse width Clock behavior Clock behavior Set the receive clock mode Set the receive clock mode Set the receive clock polarity Set the receive clock polarity Set the SRG clock divide-down value Set the SRG clock divide-down value Set the SRG clock synchronization mode Set the SRG clock synchronization mode Set the SRG clock mode [choose an input clock] Set the SRG clock mode [choose an input clock] Set the SRG input clock polarity Set the SRG input clock polarity

58 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 58 Configuration of the McBSP with CSL Example of the DSK-CCS tutorial audioIO.c of Chapter 4 for the C5416. Example of the DSK-CCS tutorial audioIO.c of Chapter 4 for the C5416. First we examine the file audioIOcfg_c.c that configures the DSP, First we examine the file audioIOcfg_c.c that configures the DSP, Then we explain how to automatically generate it with the GUI interface of CCS. Then we explain how to automatically generate it with the GUI interface of CCS. Parameters: Parameters: The McBSP 2 is used The McBSP 2 is used Single phase mode Single phase mode 32 bits words. 32 bits words. List of files of the example to examine List of files of the example to examine audioIOcfg.h audioIOcfg.h audioIOcfg_c.c audioIOcfg_c.c

59 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 59 File audioIOcfg.h Includes the Chip Support Library for the McBSP Defines variables

60 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 60 Example of McBSP configuration file 1st part of the file audioIOcfg_c.c SPCR1=0, SPCR2=0x200 All receive channel enable registers RCERx are set to 0 RCR1=0x00a0, RCR2=0 XCR1=0x00a0, XCR2=0 SRGR1=0x1f00, SRGR2=0x003f MCR1=0x0000, MCR2=0x0000 PCR=0x0083

61 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 61 Example of McBSP Configuration File Last Part of the File All transmit channel enable registers XCERx are set to 0 Using CSL to open and initialise the McBSP 2.

62 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 62 File audioIOcfg_c.c 1 of 3 SPCR1 = 0, SPCR2 = 0x0200, Serial Port Control Registers SPCR1 = 0, SPCR2 = 0x0200, Serial Port Control Registers RJUST=0, CLKSTP=0, DXENA=0, RINTM=0, RSYNCERR=0, RRST=0 RJUST=0, CLKSTP=0, DXENA=0, RINTM=0, RSYNCERR=0, RRST=0 FREE=1, SOFT=0, FRST=GRST=XINTM=XSYNCERR,XRST=0 FREE=1, SOFT=0, FRST=GRST=XINTM=XSYNCERR,XRST=0 RCR1 = 0x00A0, RCR2 = 0, Receive Control Registers RCR1 = 0x00A0, RCR2 = 0, Receive Control Registers RWDLEN1=101 = 32 bits words, RFLEN1=0 = 1 word per frame RWDLEN1=101 = 32 bits words, RFLEN1=0 = 1 word per frame RDATDLY=0, 0 bit data delay RDATDLY=0, 0 bit data delay RFIG=0, received frame-sync not ignored RFIG=0, received frame-sync not ignored RCOMPAND=0, no companding RCOMPAND=0, no companding RWLEN2=0 RWLEN2=0 RFRLEN2= 0 RFRLEN2= 0 RPHASE = 0 = 1 phase per frame, RWLEN2 and RFRLEN2 ignored. RPHASE = 0 = 1 phase per frame, RWLEN2 and RFRLEN2 ignored. XCR1 = 0x00A0, XCR2 =0 same remarks as for RCR, Transmit Control Register. XCR1 = 0x00A0, XCR2 =0 same remarks as for RCR, Transmit Control Register.

63 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 63 File audioIOcfg_c.c 2 of 3 SRGR1 = 0x1F00, SRGR2 = 0x003F, Sample Rate Generator Registers SRGR1 = 0x1F00, SRGR2 = 0x003F, Sample Rate Generator Registers CLKGDV =0, divide down value for CLKG CLKGDV =0, divide down value for CLKG FWID = 0x1F=31, frame-sync pulse width for FSG = 32 CLKG cycles FWID = 0x1F=31, frame-sync pulse width for FSG = 32 CLKG cycles FPER=0x3F=63, Frame-sync period bits for FSG, the period between frame-sync pulses on FSG is 64 CLKG cycles. FPER=0x3F=63, Frame-sync period bits for FSG, the period between frame-sync pulses on FSG is 64 CLKG cycles. FSGM=0, if FSXM=1 in PCR, the McBSP generates a frame-sync pulse when DXR is copied in XSR. But here FSXM=0 (see PCR). FSGM=0, if FSXM=1 in PCR, the McBSP generates a frame-sync pulse when DXR is copied in XSR. But here FSXM=0 (see PCR). CLKSM=0, the input clock for SRGR is taken on CLKS pin or CLKR pin depending on SCLKME bit in PCR. Here SCLKME=1=signal on CLKR. CLKSM=0, the input clock for SRGR is taken on CLKS pin or CLKR pin depending on SCLKME bit in PCR. Here SCLKME=1=signal on CLKR. CLKSP=0, CLKS pin polarity, the rising edge on CLKS pin drives the clock signal CLKG and FSG. CLKSP=0, CLKS pin polarity, the rising edge on CLKS pin drives the clock signal CLKG and FSG. GSYNC=0, no clock synchronization GSYNC=0, no clock synchronization MCR1 = 0, MCR2 = 0, no multichannel selection, Multichannel Control Registers MCR1 = 0, MCR2 = 0, no multichannel selection, Multichannel Control Registers

64 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 64 File audioIOcfg_c.c 3 of 3 PCR = 0x0083, Pin control Register PCR = 0x0083, Pin control Register CLKRP=1, CLKXP=1, clock polarity CLKRP=1, CLKXP=1, clock polarity As CLKRM=0, CLKR is an input and the received data is sampled on the rising edge of CLKR. As CLKRM=0, CLKR is an input and the received data is sampled on the rising edge of CLKR. transmit data is driven on falling edge of CLKX. transmit data is driven on falling edge of CLKX. FSRP=FSXP=0, frame-sync pulses are active high. FSRP=FSXP=0, frame-sync pulses are active high. DRSTAT=0, DXSTAT=0, not applicable here. DRSTAT=0, DXSTAT=0, not applicable here. CLKSTAT=0,not applicable here. CLKSTAT=0,not applicable here. SCLKME=1, SRGR input clock is taken from CLKR pin (CLKSM=0). SCLKME=1, SRGR input clock is taken from CLKR pin (CLKSM=0). CLKRM=CLKXM=0, not in DLB so the CLKR and CLKX pins are inputs that suppies the internal clocks. CLKRM=CLKXM=0, not in DLB so the CLKR and CLKX pins are inputs that suppies the internal clocks. FSRM=FSXM=0, Receive and transmit frame-sync is supplied by an ext source via FSR and FSX pins. FSRM=FSXM=0, Receive and transmit frame-sync is supplied by an ext source via FSR and FSX pins. RIOEN=XIOEN=0, the McBSP pins are not GPIO pins RIOEN=XIOEN=0, the McBSP pins are not GPIO pins IDLEEN=0, the McBSP remains active when the PERIPH domain is idled. IDLEEN=0, the McBSP remains active when the PERIPH domain is idled. RCERx and XCREx = 0, There is no multichannel selection RCERx and XCREx = 0, There is no multichannel selection

65 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 65 Example using the C5416 DSK 1 of 2 Create a new project iomcbsp.pjt and Create a new cdb file Create a new project iomcbsp.pjt and Create a new cdb file

66 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 66 Example using the C5416 DSK 2 of 2 Save (File>Save) the new configuration file under the project directory: iomcbsp.cdb Save (File>Save) the new configuration file under the project directory: iomcbsp.cdb Add to the project two of the files generated at the previous step: the configuration file (*.cdb) and the linker command file (*.cmd). Add to the project two of the files generated at the previous step: the configuration file (*.cdb) and the linker command file (*.cmd). Copy the file audioIO.c of chapter example in the project directory and rename it iomcbsp.c Copy the file audioIO.c of chapter example in the project directory and rename it iomcbsp.c Modify the main source file: iomcbsp to include the header file iomcbspcfg.h generated at the configuration step Modify the main source file: iomcbsp to include the header file iomcbspcfg.h generated at the configuration step and add iomcbsp.c to the project. and add iomcbsp.c to the project. Modify build options: Modify build options: Project>Build Options to add the dsk5416f.lib library and set use far calls. Project>Build Options to add the dsk5416f.lib library and set use far calls.

67 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 67 Configuring the McBSP using the McBSP Configuration Manager of the CSL GUI

68 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 68 Configuring the McBSP using the CSL GUI 1 of 4

69 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 69 Configuring the McBSP using the CSL GUI 2 of 4

70 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 70 Configuring the McBSP using the CSL GUI 3 of 4

71 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 71 Configuring the McBSP using the CSL GUI 4 of 4 Modify: Modify: « Receive Lengths », « Transmit Lengths » to set word length to 32 bits « Receive Lengths », « Transmit Lengths » to set word length to 32 bits « Sample_Rate Gen », « Sample_Rate Gen », choose generator clock source=BCLKR choose generator clock source=BCLKR set frame width to 32 and frame period to 64. set frame width to 32 and frame period to 64. « Transmit Mode », clock polarity = falling edge « Transmit Mode », clock polarity = falling edge « General » « General » Set Breakpoint Emulation to do not stop to set FREE = 1. Set Breakpoint Emulation to do not stop to set FREE = 1. Save the new iomcbsp.cdb file and look at the iomcbspcfg_c.c file. It should be quite similar to the audioIOcfg_c.c file for the initialization part. Save the new iomcbsp.cdb file and look at the iomcbspcfg_c.c file. It should be quite similar to the audioIOcfg_c.c file for the initialization part.

72 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 72 View of iomcbspcfg_c.c file at this Step

73 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 73 Configuring the McBSP using the Resource Manager of the CSL GUI Use the McBSP Resource Manager menu to generate the MCBSP_open()and the MCBSP_config() CSL functions. Use the McBSP Resource Manager menu to generate the MCBSP_open()and the MCBSP_config() CSL functions. It allows to select, open, initialize a device It allows to select, open, initialize a device We select McBSP 2 We select McBSP 2 We ask for the McBSP handle creation with the name C54XX_DMA_MCBSP that will be used by the routines of the BSL. We ask for the McBSP handle creation with the name C54XX_DMA_MCBSP that will be used by the routines of the BSL. And we ask for the opening of the McBSP handle and for the pre-initialization with object mcbspCfg0. And we ask for the opening of the McBSP handle and for the pre-initialization with object mcbspCfg0.

74 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 74 Configuring the McBSP using the CSL GUI 1 of 4

75 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 75 Configuring the McBSP using the CSL GUI 2 of 4

76 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 76 Configuring the McBSP using the CSL GUI 3 of 4

77 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 77 Configuring the McBSP using the CSL GUI 4 of 4 Save the file iomcbsp.cdb Save the file iomcbsp.cdb Open the file iomcbspcfg_c.c Open the file iomcbspcfg_c.c You should see the instructions for the opening and initialization of the McBSP. You should see the instructions for the opening and initialization of the McBSP.

78 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 78 Final version of the iomcbspcfg_c.c File Opening and initialization of McBSP2 Creation of the McBSP handle

79 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 79 Test the iomcbsp program Build the project Build the project Load iomcbsp.out in Program memory Load iomcbsp.out in Program memory Check the program Check the program using a microphone (or a CD output) and earphones, you should hear the input (mike or CD) in the earphones (or loudspeaker). using a microphone (or a CD output) and earphones, you should hear the input (mike or CD) in the earphones (or loudspeaker). Use tools>C54xx McBSP to view all the registers of the McBSP. Use tools>C54xx McBSP to view all the registers of the McBSP.

80 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 80References Users guides Users guides Spru302: Spru302: TMS320C54x DSP Reference Set Volume 5: Enhanced Peripherals. TMS320C54x DSP Reference Set Volume 5: Enhanced Peripherals. Tms320c5416.pdf Tms320c5416.pdf Spru592a: Spru592a: TMS320VC5501/5502/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide. TMS320VC5501/5502/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide.


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