2Differences between C5416 and C5510 Configuration with CSL OutlineApplication of McBSPMcBSP onC5416 and C5510Differences between C5416 and C5510Configuration with CSLReferences
3Application of McBSP McBSP = Multichannel Buffered Serial Port Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected A/D - D/A and serial devices.Direct connection to other C5000 devices,Usually works in connection with DMADepending on the specific device, the ‘C54x digital signal processor providesmultiple high-speed, full-duplex, multichannel buffered serial ports (McBSPs)that allow direct interface to other ’C54x devices, codecs and other devices ina system. The ’C5402 provides two, the ’C5410 three, and the ’C5420 six McBSPs.They are based on the standard serial port interface found on other ’C54x devices.
4Audio System using DMA and McBSP Here the codec means Coder Decoder.Let’s take a closer look at how the buffers are organized...
5What about the output buffers? Ping-Pong BuffersIn order to make the application less real-time critical, the input is double bufferedThese buffers are called ping-pong buffersThe configuration is that of a two frame circular bufferFirst fill one buffer, then fill the other, then switch back to the firstWhat about the output buffers?
6What needs to happen to the DMA Channels? The Flow 1 of 4What needs to happen to the DMA Channels?
7What buffers can the application use to process? The Flow 2 of 4What buffers can the application use to process?
8How do we know when new buffers are ready? The Flow 3 of 4How do we know when new buffers are ready?
9And everything starts over…on to the hardware!! The Flow 4 of 4And everything starts over…on to the hardware!!
10McBSP on C5416 and C5510 C5416 and C5510 McBSP are very similar The small differences will be discussed in a later section3 McBSPs on C5416 and C5510Basic pins on serial ports (R for Read and X for Transmit):BDR or BDX: serial dataBCLKR or BCLKX: clock at bit rateBFSR or BFSX: frame synchronization (word rate)
11Multi-Channel Buffered Serial Port (McBSP) The McBSP consists of a data path and a control path connected to externaldevices by seven pins.There are actually two DRR and 2 DXR registers (DRR1, DRR2, DXR1, DXR2), each 16-bits wide.But only ONE register is shown here that can accommodate data from 8 to 32 bits.DRR2, RBR2, RSR2, DXR2, and XSR2 registers are not utilized (written, read,or shifted) if the receive/transmit word length, R/XWDLEN[1,2], is specified for8-, 12-, or 16-bit mode.Data are communicated to devices interfacing the McBSP via the data transmit(DX) pin for transmit and the data receive (DR) pin for receive. Control informationin the form of clocking and frame synchronization is communicated viaCLKX, CLKR, FSX, and FSR. The ’C54x communicates with the McBSP through16-bit-wide control registers accessible via the internal peripheral bus.The CPU or the DMA controller reads the received data from the data receiveregister (DRR[1,2]) and writes the data to be transmitted to the data transmitregister (DXR[1,2]). Data written to DXR[1,2] is shifted out to DX via the transmitshift register (XSR[1,2]). Similarly, receive data on the DR pin is shifted intothe receive shift register (RSR[1,2]) and copied into the receive buffer register(RBR[1,2]). RBR[1,2] is then copied to DRR[1,2], which can be read by the CPUor the DMA controller. This allows simultaneous movement of internal and externaldata communications.Full duplex, max bit rate = ½ CPU clockWord length: 8, 12, 16,20, 24, 32Frame length (between FS): words
12McBSP Interface Signals The receive operation is triple buffered and the transmit operation is double buffered.Receive data arrive on DR and are shifted into RSR[1,2]. Once a full word (8-,12-, 16-, 20-, 24-, or 32-bit) is received, RSR[1,2] is copied to the receive bufferregister, RBR[1,2], only if RBR[1,2] is not full. RBR[1,2] is then copied toDRR[1,2], unless DRR[1,2] is not read by the CPU or DMA.Transmit data is written by the CPU or DMA to DXR[1,2]. If there is no data inXSR[1,2], the value in DXR[1,2] is copied to XSR[1,2]; otherwise, DXR[1,2] iscopied to XSR[1,2] when the last bit of data is shifted out from DX. After transmitframe synchronization, XSR[1,2] begins shifting out the transmit data from DX.
13More Features of the McBSP 1 of 2 Double-buffered transmission and triple-buffered receptionIndependent clocking and framing for transmit and receive.Capability to send interrupts to the CPU and DMA event to the DMA controller.External shift clock generation or an internal programmable-frequency clockHighly programmable internal clock and frame generationProgrammable sample rate generator128 channels.In addition, the McBSP has the following capabilities:Direct interface to:T1/E1 framersMVIP switching compatible and ST-BUS compliant devices including:MVIP framersH.100 framersSCSA framersIOM-2 compliant devicesAC97 compliant devices (the necessary multi-phase frame-synchronization capability is provided.)IIS compliant devicesSPI devices
14More Features of the McBSP 2 of 2 Programmable polarity for both frame synchronization and data clocks8-bit data transfers with option of LSB or MSB first-Law and A-Law compandingCompanding (COMpress and exPAND) hardware allows compression and expansionof data in either -law or A-law format. The companding standardemployed in the United States and Japan is -law. The European compandingstandard is referred to as A-law. The specification for -law and A-law log PCMis part of the CCITT G.711 recommendation.A-law and -law allows 13 bits and 14 bits of dynamic range, respectively. Any values outside this range willbe set to the most positive or most negative value. Thus, for companding towork best, the data transferred to and from the McBSP via the CPU or DMAmust be at least 16-bit wide data.The -law and A-law formats encode data into 8-bit code words. Compandeddata is always 8-bits wide; therefore, the appropriate (R/X)WDLEN[1,2] mustbe set to 0, indicating 8-bit wide serial data stream. If companding is enabledand either phase of the frame does not have 8-bit word length, then compandingcontinues as if the word length is eight bits.When companding is used, transmit data is encoded according to specifiedcompanding law, and receive data is decoded to 2’s complement format. Compandingis enabled and the desired format selected by appropriately setting(R/X)COMPAND in (R/X)CR2.Compression occurs during the process of copying data from DXR1-to-XSR1and from RBR1-to-DRR1,For transmit data to be compressed properly, the data should be left-justifiedwhen it is written to DXR1. When using m-law, the 14 data bits are left-justifiedin the register, with the remaining two low-order bits filled with zeros.Companding internal dataIf the McBSP is otherwise unused (serial port X/R sections are reset), the compandinghardware can compand internal data. This can be used to:Convert linear to the appropriate m-law or A-law format.Convert m-law or A-law to the linear format.Observe the quantization effects in companding by transmitting lineardata, and compressing and re-expanding this data. This is only useful ifboth XCOMPAND and RCOMPAND enable the same companding format.There are 2 methods by which the McBSP can compand internaldata. Data paths for these two methods are used to indicate:1) When both the transmit and receive sections of the serial port are reset,DRR1 and DXR1 are internally connected through the companding logic.Values from DXR1 are compressed, as selected by XCOMPAND, andthen expanded, as selected by RCOMPAND. Note that RRDY and XRDYbits are not set. However, data is available in DRR1 within four CPU clocksafter being written to DXR1. The advantage of this method is its speed.The disadvantage is that there is no synchronization available to the CPUand DMA to control the flow. Note that DRR1 and DXR1 are internally connectedif the (X/R)COMPAND bits are set to 1xb, i.e., compand using Alawor m-law.2) The McBSP is enabled in digital loop back mode with companding appropriatelyenabled by RCOMPAND and XCOMPAND. Receive and transmitinterrupts (RINT when RINTM = 0 and XINT when XINTM = 0) or synchronizationevents (REVT and XEVT) allow synchronization of the CPU orDMA to these conversions, respectively. Here, the time for this compandingdepends on the serial bit rate selected.
15Bit OrderingNormally, transfers using the McBSP are sent and received with the MSB first.Certain 8-bit data protocols (that do not use companded data) require the LSB to be transferred first:By setting (R/X)COMPAND = 01b in (R/X)CR2, the bit ordering of 8-bit words is reversed (LSB first) .This feature is only enabled if the appropriate (R/X)WDLEN[1,2] is set to 0, (8-bit words).If either phase of the frame does not have an 8-bit word length, the McBSP assumes the word length is 8 bits, and LSB-first ordering is done.
16McBSP Data and Control Paths The letter B before the pin names is omitted on this figure, ie DX instead of BDX.It will also be the case in the following slides.Apart from the data registers DRR1, DRR2, DXR1, DXR2,XSR[1,2]). RSR[1,2] and RBR[1,2]), the McBSP includes control registers.These registers are accessible to the CPU to configure the control mechanismof the McBSP.The control block consists of internal clock generation, frame-synchronizationsignal generation, and their control and multichannel selection.This control block sends notification of important events to the CPU and DMAcontroller via the two interrupt and four event signals.
17McBSP Control Registers for Clock and Frame Synchronisation and Control The x at the end of a register name represents the number of the McBSP device: McBSP 0,1 or 2.
18McBSP Control Registers for Channel Selection 8 partitions A, B, C, D, E, F, G, HEarlier versions of ‘C54 such as ‘C5410 or ‘C5420 only contained partitions A and B.The x at the end of a register name represents the number of the McBSP device: McBSP 0,1 or 2.
19McBSP Configuration Via SPCR1, SPCR2 and PCR registers These contain status information and bits that can be configured for the required operation.PCRConfigures the McBSP pins as inputs or outputs during normal serial port operation,Configures the pins as general purpose inputs or outputs during receiver and/or transmitter reset.
20Configuration of McBSP, SPCR1 Register DLB= Digital Loop Back ModeRJUST = Receive Sign-Extension and Justification ModeCLKSTP = Clock Stop ModeDXENA = DX delay EnablerABIS = A-bis modeRINTM = Receive Interrupt ModeRSYNCERR = Receive Synchronization ErrorRFULL = Receiver shift Register fullRRDY = Receiver ReadyRRST = Receiver ResetDLP = Digital Loop Back ModeDLB = 0 Digital loop back mode disabledDLB = 1 Digital loop back mode enabledRJUST Receive Sign-Extension and Justification ModeRJUST = 00 Right-justify and zero-fill MSBs in DRR[1,2]RJUST = 01 Right-justify and sign-extend MSBs in DRR[1,2]RJUST = 10 Left-justify and zero-fill LSBs in DRR[1,2]RJUST = 11 ReservedRJUST in SPCR1 selects whether data in RBR[1,2] is right or left justified (withrespect to the MSB) in DRR[1,2]. If right-justification is selected, RJUST furtherselects whether the data is sign-extended or zero-filled.CLKSTP Clock Stop ModeCLKSTP = 0X Clock stop mode disabled. Normal clocking for non-SPI mode.Various SPI modes when:CLKSTP = 10 andCLKXP = 0Clock starts with rising edge without delayCLKXP = 1Clock starts with falling edge without delayCLKSTP = 11 andClock starts with rising edge with delayClock starts with falling edge with delayDXENA DX Enabler.DXENA = 0 DX enabler is offDXENA = 1 DX enabler is onABIS ModeABIS = 0 A-bis mode is disabledABIS = 1 A-bis mode is enabledRINTM Receive Interrupt ModeRINTM = 00 RINT driven by RRDY (i.e. end of word) and end offrame in A-bis mode.RINTM = 01 RINT generated by end-of-block or end-of-frame inmultichannel operationRINTM = 10 RINT generated by a new frame synchronizationRINTM=11 RINT generated by RSYNCERRRSYNCERR Receive Synchronization ErrorRSYNCERR = 0 No synchronization errorRSYNCERR = 1 Synchronization error detected by McBSP.RFULL Receive Shift Register (RSR[1,2]) FullRFULL = 0 RBR[1,2] is not in overrun conditionRFULL = 1 DRR[1,2] is not read, RBR[1,2] is full and RSR[1,2]is also full with new wordRRDY Receiver ReadyRRDY = 0 Receiver is not ready.RRDY = 1 Receiver is ready with data to be read from DRR[1,2].RRST Receiver reset. This resets and enables the receiver.RRST = 0 The serial port receiver is disabled and in reset state.RRST = 1 The serial port receiver is enabled.
21Configuration of McBSP, SPCR2 Register FREE = Free Running mode (in emulation)SOFT = Soft bit (in emulation)FRST = Frame-sync generator ResetGRST = Sample rate generator ResetFREE Free Running ModeFREE = 0 Free running mode is disabledFREE = 1 Free running mode is enabledSOFT Soft BitSOFT = 0 SOFT mode is disabledSOFT = 1 SOFT mode is enabledFRST Frame-Sync Generator ResetFRST = 0 Frame-synchronization logic is reset. Frame-syncsignal FSG is not generated by the sample-rate generator.FRST = 1 Frame-sync signal FSG is generated after(FPER+1) number of CLKG clocks; i.e., all framecounters are loaded with their programmed values.GRST Sample-Rate Generator ResetGRST = 0 Sample rate generator is resetGRST = 1 Sample rate generator is pulled out of reset. CLKGis driven as per programmed value in sample rategenerator registers (SRGR[1,2]).
22Configuration of McBSP PCR Pin Control Register XIOEN = Transmit general purpose IO modeRIOEN = Receive general purpose IO modeFSXM = Transmit Frame-Synchronization ModeFSRM = Receive Frame-Synchronization ModeCLKXM, CLKRM = Transmitter (Receiver) clock ModeCLKS_STAT = Status of CLKS pin when GPIODX_STAT, DR_STAT = Status of DX (DR) when GPIOFSXP, FSRP = Transmit (receive) Frame-Sync. PolarityCLKXP, CLKRP = Transmit (receive) Clock PolarityXIOEN Transmit general purpose I/O mode only when XRST = 0 in SPCR[1,2]XIOEN = 0 DX, FSX and CLKX are configured as serial port pins anddo not function as general-purpose I/Os.XIOEN = 1 DX pin is a general purpose output. FSX and CLKX aregeneral purpose I/Os. These serial port pins do notperform serial port operation.RIOEN Receive general purpose I/O mode only when RRST = 0 in SPCR[1,2]RIOEN = 0 DR, FSR, CLKR and CLKS are configured as serial portpins and do not function as general-purpose I/Os.RIOEN = 1 DR and CLKS pins are general purpose inputs; FSR andCLKR are general purpose I/Os. These serial port pins donot perform serial port operation. The CLKS pin is affectedby a combination of RRST and RIOEN signals of thereceiver.FSXM Transmit Frame-Synchronization ModeFSXM = 0 Frame-synchronization signal derived from an external sourceFSXM = 1 Frame synchronization is determined by the sample rategenerator frame-synchronization mode bit FSGM in SRGR2.FSRM Receive Frame-Synchronization ModeFSRM = 0 Frame-synchronization pulses generated by an externaldevice. FSR is an input pinFSRM = 1 Frame synchronization generated internally by samplerate generator. FSR is an output pin except whenGSYNC=1 in SRGR.CLKXM Transmitter Clock ModeCLKXM = 0 Transmitter clock is driven by an external clock with CLKXas an input pin.CLKXM = 1 CLKX is an output pin and is driven by the internal samplerate generator.During SPI mode (when CLKSTP is a non-zero value):CLKXM = 0 McBSP is a slave and clock (CLKX) is driven by the SPImaster in the system. CLKR is internally driven by CLKX.CLKXM = 1 McBSP is a master and generates the clock (CLKX) todrive its receive clock (CLKR) and the shift clock of theSPI-compliant slaves in the system.CLKRM Receiver Clock ModeCase 1: Digital loop back mode not set (DLB = 0) in SPCR1CLKRM = 0 Receive clock (CLKR) is an input driven by an external clock.CLKRM = 1 CLKR is an output pin and is driven by the internal sampleCase 2: Digital loop back mode set (DLB=1) in SPCR1CLKRM = 0 Receive clock (not the CLKR pin) is driven by transmitclock (CLKX) which is based on the CLKXM bit in the PCR.CLKR pin is in high-impedance.CLKRM = 1 CLKR is an output pin and is driven by the transmit clock.The transmit clock is derived based on the CLKXM bit in the PCR.CLKS_ STAT CLKS pin status. Reflects value on CLKS pin when selected as a generalpurpose input.DX_STAT DX pin status. Reflects value driven on to DX pin when selected as a general purpose output.DR_STAT DR pin status. Reflects value on DR pin when selected as a general purpose input.FSXP Transmit Frame-Synchronization PolarityFSXP = 0 Frame-synchronization pulse FSX is active highFSXP = 1 Frame-synchronization pulse FSX is active lowFSRP Receive Frame-Synchronization Polarity FSRP = 0 Frame-synchronization pulse FSR is active highFSRP = 1 Frame-synchronization pulse FSR is active lowCLKXP Transmit Clock PolarityCLKXP = 0 Transmit data sampled on rising edge of CLKXCLKXP = 1 Transmit data sampled on falling edge of CLKXCLKRP Receive Clock PolarityCLKRP = 0 Receive data sampled on falling edge of CLKRCLKRP = 1 Receive data sampled on rising edge of CLKR
23Receive and Transmit Control Registers RCR and XCR RFLEN1 = Receive Frame Length 1 (1 to 128 words / frame)RWDLEN1 = Receive Word Length 1 (8, 12, 16, 20, 24, 32 bits)RCR2RPHASE = Receive phases (single or dual frames)RFLEN2 =Receive Frame Length 2 (1 to 128 words / frame)RWDLEN2 = Receive Word Length 2 (8, 12, 16, 20, 24, 32 bits)RCOMPAND = Receive companding modeRFIG = Receive Frame IgnoreRDATDLY =Receive Data DelayThe receive and transmit control registers (RCR[1,2] and XCR[1,2]) configurevarious parameters of the receive and transmit operations, respectively.RCR1RFRLEN1 Receive Frame LengthRFRLEN1 = word per frameRFRLEN1 = words per frame….RFRLEN1 = words per frameRWDLEN1 Receive Word LengthRWDLEN1 = bitsRWDLEN1 = bitsRWDLEN1 = bitsRWDLEN1 = bitsRWDLEN1 = bitsRWDLEN1 = bitsRWDLEN1 = 11X ReservedRCR2------RPHASE Receive PhasesRPHASE = 0 Single-phase frameRPHASE = 1 Dual-phase frameRFRLEN2 Receive Frame LengthRFRLEN2 = word per frameRFRLEN2 = words per frameRFRLEN2 = words per frameRWDLEN2 Receive Word Length 2RWDLEN2 = bitsRWDLEN2 = bitsRWDLEN2 = bitsRWDLEN2 = bitsRWDLEN2 = bitsRWDLEN2 = bitsRWDLEN2 = 11X reservedRCOMPAND Receive companding mode. Modes other than 00b are only enabledwhen the appropriate RWDLEN is 000b, indicating 8-bit data.RCOMPAND = 00 No companding, data transfer starts with MSB first.RCOMPAND = 01 No companding, 8-bit data, PHASE: trannsfer starts with LSB first.RCOMPAND = 10 Compand using m-law for receive data.RCOMPAND = 11 Compand using A-law for receive data.RFIG Receive Frame IgnoreRFIG = 0 Receive frame-synchronization pulses after the first restarts the transfer.RFIG = 1 Receive frame-synchronization pulses after the first are ignored.RDATDLY Receive data delayRDATDLY = 00 0-bit data delayRDATDLY = 01 1-bit data delayRDATDLY = 10 2-bit data delayRDATDLY = 11 ReservedRFIGThe McBSP can be configured to ignore transmit and receive frame-synchronizationpulses. The (R/X)FIG bit in (R/X)CR2 can be programmed to zero torecognize frame-sync pulses, or set to one to ignore frame-sync pulses. Theuser can use (R/X)FIG bit to either pack data or ignore unexpected frame-syncpulses.Structure of XCR1 and XCR2 is similar to that of RCR1 and RCR2.
24McBSP Reset (R/X)RST and RESET Device reset (RS = 0) places the receiver, transmitter and the sample rate generator SRGR in reset.When the device reset is removed (RS = 1) GRST = FRST = RRST = XRST = 0, keeping the entire serial port in the reset state.The SP transmitter and receiver can be independently reset by the RRST and XRST bits in the SPCR registers. The SRGR is reset by the GRST bit in SPCR2.
25Determining Ready Status RRDY and XRDY indicate the ready state of the McBSP receiver and transmitter.Serial port writes and reads may be synchronized:By polling RRDY and XRDY,or by using the events to DMAREVT and XEVT in normal mode,and REVTA and XEVTA in A-bis mode,or by interrupts to CPU (RINT and XINT), which the events generate.Note that reading DRR[1,2] and writing to DXR[1,2] affect RRDY and XRDY.Receive Ready Status: REVT, RINT, and RRDYRRDY = 1 indicates that the RBR[1,2] contents have been copied to DRR[1,2]and that the data can be read by the CPU or DMA. Once that data has beenread by either the CPU or DMA, RRDY is cleared to 0. Also, at device resetor serial port receiver reset (RRST = 0), RRDY is cleared to 0 to indicate nodata has yet been received and loaded into DRR[1,2]. RRDY directly drivesthe McBSP receive event to the DMA (REVT). Also, the McBSP receive interrupt(RINT) to the CPU may be driven by RRDY, if RINTM = 00b in SPCR1.Transmit Ready Status: XEVT, XINT, and XRDYXRDY = 1 indicates that the DXR[1,2] contents have been copied to XSR[1,2]and that DXR[1,2] is ready to be loaded with a new data word. When the transmittertransitions from reset to non-reset (XRST transitions from 0 to 1), XRDYalso transitions from 0 to 1 indicating that DXR[1,2] is ready for new data. Oncenew data is loaded by the CPU or DMA, XRDY is cleared to 0. However, oncethis data is copied from DXR[1,2] to XSR[1,2], XRDY transitions again from 0to 1. Now once again, the CPU or DMA can write to DXR[1,2] althoughXSR[1,2] has not been shifted out on DX yet. XRDY directly drives the transmitsynchronization event to the DMA (XEVT or XEVTA). In addition, the transmitinterrupt (XINT) to the CPU may also be driven by XRDY, if XINTM = 00b inSPCR2.
26Frame and Clock Configuration The McBSP allows independent configurations of data clock and frame synchronization for receive and transmit:Polarities of FSR, FSX, CLKX, and CLKRA choice of single- or dual-phase framesFor each phase, the number of words per frameFor each phase, the number of bits per wordSubsequent frame synchronization may restart the serial data stream or be ignored.The data bit delay from frame synchronization to first data bit can be 0-,1-, or 2-bit delays.Right- or left-justification as well as sign-extension or zero-filling can be chosen for receive data.Serial clocks CLKR, and CLKX define the boundaries between bits forreceive and transmit, respectively. Similarly, frame-sync signals FSR and FSXdefine the beginning of a serial word.
27Frame and Clock Operation Receive and transmit frame-sync pulses can be generated:Either internally by the sample rate generator SRGR,or driven by an external source.The source of frame sync is selected by the mode bit, FS(R/X)M, in the PCR.FSR is affected by GSYNC bit in SRGR2Receive and transmit clocks can be selected to be inputs or outputs by the mode bit, CLK(R/X)M, in the PCR.Receive and transmit frame-sync pulses can be generated either internally bythe sample rate generator (see section 2.5.1, Sample Rate Generator Clockingand Framing, on page 2-58) or driven by an external source. The sourceof frame sync is selected by programming the mode bit, FS(R/X)M, in the PCR.FSR is also affected by the GSYNC bit in SRGR2 (for details, see section, Receive Frame-Sync Selection: DLB, FSRM, GSYNC, on page 2-67).Similarly, receive and transmit clocks can be selected to be inputs or outputsby programming the mode bit, CLK(R/X)M, in the PCR.When FSR and FSX are inputs (FSXM=FSRM=0, external frame-syncpulses), the McBSP detects them on the internal falling edge of clock, internalCLKR, and internal CLKX, respectively (see Figure 2–41, Clock and FrameGeneration, on page 2-57). The receive data arriving at the DR pin is alsosampled on the falling edge of internal CLKR. Note that these internal clocksignals are either derived from external source via CLK(R/X) pins or driven bythe sample rate generator clock (CLKG) internal to the McBSP.
28Sample Rate GeneratorThe sample rate generator is composed of a three-stage clock divider that allowsprogrammable data clocks (CLKG) and framing signals (FSG).CLKG and FSG are McBSP internal signals that can be programmedto drive receive and/or transmit clocking (CLKR/X) and framing (FSR/X).The sample rate generator can be programmed to be driven by aninternal clock source or an internal clock derived from an external clock source.The three stages of the sample rate generator circuit compute the following:- Clock divide down (CLKGDV): The number of input clocks per data bit clock.- Frame period divide down (FPER): The frame period in data bit-clocks.- Frame width count down (FWID): The width of an active frame pulse indata bit-clocks.In addition, a frame pulse detection and clock synchronization module allowssynchronization of the clock divide down with an incoming frame pulse.
29Sample Rate Generator Register SRGR FWID = Frame WidthCLKGDV = Sample rate generator Clock DividerSRGR 2GSYNC = SRGR Clock synchronizationCLKSP = Polarity Clock edge selectionCLKSM = SRGR Clock ModeFSGM = SRGR transmit Frame-Sync ModeFPER = Frame PeriodSRGR1FWID Frame Width.This field plus 1 determines the width of the frame-sync pulse, FSG, during its active period.Range: up to 2; 1 to 256 CLKG periods.CLKGDV Sample Rate Generator Clock DividerThis value is used as the divide-down number to generate the requiredsample rate generator clock frequency. Default value is 1.SRGR2GSYNC Sample Rate Generator Clock SynchronizationOnly used when the external clock (CLKS) drives the sample rate generatorclock (CLKSM=0).GSYNC = 0 The sample rate generator clock (CLKG) is free running.GSYNC = 1 The sample rate generator clock (CLKG) is running. ButCLKG is resynchronized and frame-sync signal (FSG) isgenerated only after detecting the receiveframe-synchronization signal (FSR). Also, frame period,FPER, is a don’t care because the period is dictated by theexternal frame-sync pulse.CLKSP CLKS Polarity Clock Edge SelectOnly used when the external clock CLKS drives the sample rate generatorclock (CLKSM = 0).CLKSP = 0 Rising edge of CLKS generates CLKG and FSG.CLKSP = 1 Falling edge of CLKS generates CLKG and FSG.CLKSM McBSP Sample Rate Generator Clock ModeCLKSM = 0 Sample rate generator clock derived from the CLKS pin.CLKSM = 1 Sample rate generator clock derived from CPU clock.FSGM Sample Rate Generator Transmit Frame-Synchronization ModeUsed when FSXM=1 in the PCR.FSGM = 0 Transmit frame-sync signal (FSX) due toDXR[1,2]-to-XSR[1,2] copy. When FSGM = 0, FPR andFWID are ignored.FSGM = 1 Transmit frame-sync signal driven by the sample rategenerator frame-sync signal, FSG.FPER Frame Period. This field plus 1 determines when the next frame-sync signalbecomes active.Range: 1 to 4096 CLKG periods.
30Data Clock GenerationWhen (CLK[R/X]M = 1), the data clocks (CLK[R/X]) are driven by:the internal SRGR output clock, CLKG.The input clock to the SRGR can be either the CPU clock or a dedicated external clock input (CLKS).The CLKSM bit in SRGR2 selects either the CPU clock (CLKSM = 1) or the external clock input (CLKSM = 0) CLKS.The input clock source to the SRGR can be divided down by a programmable value (CLKGDV) to drive CLKGRegardless of the source to the SRGR, the rising edge of CLKSRG generates CLKG and FSGSample Rate Generator Data Bit Clock Rate: CLKGDVThe first divider stage generates the serial data bit clock from the input clock.This divider stage utilizes a counter that is preloaded by CLKGDV which containsthe divide ratio value. The output of this stage is the data bit-clock whichis output on sample rate generator output, CLKG, and serves as the input forthe second and third divider stages.CLKG has a frequency equal to 1/(CLKGDV+1) of sample rate generator inputclock. Thus, sample generator input clock frequency is divided by a value between1 and 256. When CLKGDV is odd or equal to 0, the CLKG duty cycleis 50%. When CLKGDV is an even value, 2p, representing an odd divide down,the high-state duration is p+1 cycles and the low-state duration is pcycles.Bit Clock Polarity: CLKSPExternal clock (CLKS) is selected to drive the sample rate generator clock dividerby selecting CLKSM=0. In this case, the CLKSP bit in SRGR2 selects theedge of CLKS on which sample rate generator data bit-clock (CLKG) andframe-sync signal (FSG) are generated. Since the rising edge of CLKSRG(see Figure 2–42) generates CLKG and FSG, the rising edge of CLKS whenCLKSP = 0, or the falling edge of CLKS when CLKSP = 1, causes the transitionon the data bit-rate clock (CLKG) and frame sync (FSG).Bit Clock and Frame SynchronizationWhen CLKS is selected to drive the sample rate generator (CLKSM = 0),GSYNC can be used to configure the timing of CLKG relative to CLKS.GSYNC = 1 ensures that the McBSP, and the external device that it is communicatingto, are dividing down CLKS with the same phase relationship. IfGSYNC = 0, this feature is disabled and therefore CLKG runs freely and is notre-synchronized. If GSYNC = 1, an inactive-to-active transition on FSR triggersa resynchronization of CLKG and generation of FSG. CLKG always beginswith a high state after synchronization. Also, FSR is always detected atthe same edge of CLKS that generates CLKG, no matter how long the FSRpulse is. Although an external FSR is provided, FSG can still drive internal receiveframe synchronization when GSYNC = 1. Note that when GSYNC = 1,FPER is a don’t care because the frame period is determined by the arrival ofthe external frame-sync pulse.Figure 2–45 and Figure 2–46 show the bit clock and frame-synchronizationoperation with various polarities of CLKS and FSR. These figures assumeFWID = 0, for an FSG one CLKG wide.
31Digital Loop Back Mode DLB DLB = 1 in SPCR1 enables digital loop back mode.During DLB mode, DR, FSR, and CLKR are internally connected through multiplexers to DX, FSX, CLKX, respectively.DLB mode allows testing of serial port code with a single DSP device.In digital loop back mode, the transmitter clock drives the receiver. CLKRM determines whether the CLKR pin is an input or an output.
32Frame-sync Signal Generation When FRST=1 in SPCR2, it activates the frame-sync generation logic to generate a frame-sync signal, if FSGM = 1 in SRGR2.Frame-sync programming options:A frame pulse with a programmable period and programmable active width, using the SRGR1 register,The transmit portion may trigger its own frame-sync signal generated by a DXR[1,2]-to-XSR[1,2] copy,Both the receive and transmit sections may independently select an external frame synchronization on the FSR and FSX pins, respectively.When the transmit portion triggers its own frame-sync signal generated bya DXR[1,2]-to-XSR[1,2] copy. the data delays can be programmed as required;however, maximum frame frequency cannot be achieved in this methodfor data delays one and two. This limitation can be overcome by programmingthe frame ignore bit (R/X)FIG = 1.Frame Period and Frame Width: FPER and FWIDFPER and FWID are implemented as down-counters. The FPER stage is a12-bit down-counter that counts down the generated data clocks from 4095 to0. FPER controls the period of active frame-sync pulses. The FWID stage inthe sample rate generator is an 8-bit down counter. The FWID field controlsthe active width of the frame-sync pulse. Both these counters gets loaded withtheir respective programmed value in FPER and FWID.When the sample rate generator comes out of reset, FSG is in its inactive state.Then, when FRST = 1 and FSGM = 1, a frame sync is generated. The framewidth value (FWID+1) is counted down on every CLKG cycle until it reacheszero, when FSG goes low. Thus, the value of FWID + 1 determines an activeframe pulse width ranging from 1 to 256 data bit-clocks. At the same time, theframe period value (FPER+1) is also counting down. When this value reacheszero, FSG goes high, again indicating a new frame.It is recommended that FWID be programmed to a value less thanWDLEN[1,2].Thus, the value of FPER+1 determines a frame length from 1 to4096 data bits. When GSYNC = 1, FPER is a don’t care value. Figure 2–47shows a frame of period 16 CLKG periods (FPER = 15 or b), and aframe with an active width of 2 CLKG periods (FWID = 1).
33McBSP - ExampleProblem: transfer bit words to SARAM, ext’l CLK/FS, no CPU intOperation- Bit/CLKR shifted into RSR- RSR RBR- RBR DRR (RRDY=1)- REVT sync event activates DMA (no McBSP setup)- DMA transfers DRR to SARAM…repeat
34Multichannel Selection Operation A McBSP channel is a time slot for shifting in/out the bits of one serial word.Each McBSP supports up to 128 channels.The 128 channels are divided into 8 blocks of 16 consecutive channels:Block 0: Channels 0-15Block 1: Channels …Block 7: ChannelsThe blocks are assigned to partitions:In ‘C5410 or ‘C5420, only 2 partitions A or BIn the C5416 and C5510, choice between 2 partitions (A,B) or 8 partitions (A, B, C, …H.)Multiple channels can be independently selected for the transmitter and receiverby configuring the McBSP with a single-phase frame. Each frame representsa time-division multiplexed (TDM) data stream. The number of words perframe represented by (R/X)FRLEN1, denotes the number of channels availablefor selection.When using TDM data streams, the CPU may need to process only a few ofthem. Thus, to save memory and bus bandwidth, multichannel selection allowsindependent enabling of particular channels for transmission and reception.Up to 32 channels can be enabled in an up-to-128-channel bit-stream.
35Multichannel Partition Mode In the 2 partitions mode:One even-numbered block (0,2,4,6) is assigned to partition A and one odd-numbered block (1,3,5,7) to partition B.Up to 32 channels can be selected.In the 8 partitions mode, blocks 0 through 7 are automatically assigned to partitions A through H.Up to 128 channels can be selected.The number of partitions for reception and transmission are independent.
36Multichannel Selection When a McBSP uses a TDM (Time Division Multiplex) data stream, it may need to select only a few channels to save memory and bandwidth.Each channel partition has a dedicated channel enable register.If the multichannel selection mode is on, each bit in the register controls whether a channel is selected or not in the partition.There is 1 receive multichannel selection mode and 3 transmit modes.
37Configuring a Frame for Multichannel Selection Select a single-phase frame:RPHASE/WPHASE = 0Each frame represents a TDM data stream.Set a frame length (R/X)FRLEN1 including the highest-numbered channel in the selection.
38Control of Multichannel Selection The multichannel mode can be enabled independently for receive and transmit by setting RMCM = 1 and XMCM to a non-zero value in control registers MCR[1,2], respectively.Choose the partition mode: 2 or 8 partitions, with the RMCME and/or XMCME bits:(R/X)MCME = 0, 2 partitions A-B(R/X)MCME = 1, 8 partitions A-B…H
39Multichannel Operation Control Registers MCR1, MCR2: Multichannel control registersXCERx: transmit channel enable registersx = a letter A, B, C, D, E, F or HRCERx: receive channel enable registers
40Multichannel Operation MCR1 Register MCR1 for C5410 or C5420RPBBLK = Receive Partition B BlockRPABLK = Receive Partition A BlockRCBLK = Receive Current BlockRMCM = Receive Multichannel Selection EnableMCR1 for C5416 and C5510RMCME = Receive Multichannel Partition Mode bit, applicable if channel can be individually selected RMCM = 1MCR1RPBBLK Receive Partition B BlockRPBBLK = 00 Block 1. Channel 16 to channel 31RPBBLK = 01 Block 3. Channel 48 to channel 63RPBBLK = 10 Block 5. Channel 80 to channel 95RPBBLK = 11 Block 7. Channel 112 to channel 127RPABLK Receive Partition A BlockRPABLK = 00 Block 0. Channel 0 to channel 15RPABLK = 01 Block 2. Channel 32 to channel 47RPABLK = 10 Block 4. Channel 64 to channel 79RPABLK = 11 Block 6. Channel 96 to channel 111RCBLK Receive Current BlockRCBLK = 000 Block 0. Channel 0 to channel 15RCBLK = 001 Block 1. Channel 16 to channel 31RCBLK = 010 Block 2. Channel 32 to channel 47RCBLK = 011 Block 3. Channel 48 to channel 63RCBLK = 100 Block 4. Channel 64 to channel 79RCBLK = 101 Block 5. Channel 80 to channel 95RCBLK = 110 Block 6. Channel 96 to channel 111RCBLK = 111 Block 7. Channel 112 to channel 127RMCM Receive Multichannel Selection EnableRMCM = 0 All 128 channels enabled.RMCM = 1 All channels disabled by default. Required channels areselected by enabling RP(A/B)BLK and RCER(A/B) appropriately.RMCME Receive multichannel partition mode bit. RMCME is only applicable if channelscan be individually enabled or disabled for reception (RMCM = 1).RMCME determines whether only 32 channels or all 128 channels are tobe individually selectable.0 2-partition modeOnly partitions A and B are used. You can control up to 32 channels in thereceive multichannel selection mode (RMCM = 1).Assign 16 channels to partition A with the RPABLK bits. Assign 16 channelsto partition B with the RPBBLK bits.You control the channels with the appropriate receive channel enable registers:RCERA: Channels in partition ARCERB: Channels in partition B1 8-partition modeAll partitions (A through H) are used. You can control up to 128 channels inthe receive multichannel selection mode.RCERA: Channels 0 through 15RCERB: Channels 16 through 31RCERC: Channels 32 through 47RCERD: Channels 48 through 63RCERE: Channels 64 through 79RCERF: Channels 80 through 95RCERG: Channels 96 through 111RCERH: Channels 112 through 127
41Multichannel Operation MCR2 Register MCR2 has the same structure as MCR1 but for transmission.MCR 2 for C5410 or C54 20MCR 2 for C5416 and C5510The XMCM bits of XCR2 determine whether all channels or only selected channels are enabled and unmasked for transmission.There are 3 transmit multichannel selection modes00b: No selection. All channels are enabled and unmasked.01b: All channels are disabled unless selected in XCERs registers. If enabled, a channel is also unmasked.10b: All channels are enabled, but they are masked unless they are selected in XCERs registers.11 b: symmetric transmission/reception. All channels are disabled for transmission unless they are enabled for reception in RCER registers. Once enabled, they are masked unless they are also selected in the XCERs registers.XMCM Transmit Multichannel Selection EnableXMCM = 00 All channels enabled without masking (DX is alwaysdriven during transmission of dataXMCM = 01 All channels disabled and therefore masked by default.Required channels are selected by enabling XP(A/B)BLKand XCER(A/B) appropriately. Also, these selectedchannels are not masked and therefore DX is alwaysdriven.XMCM = 10 All channels enabled, but masked. Selected channelsenabled via XP(A/B)BLK and XCER(A/B) are unmasked.XMCM = 11 All channels disabled and therefore masked by default.Required channels are selected by enablingRP(A/B)BLK and RCER(A/B) appropriately. Selectedchannels can be unmasked by RP(A/B)BLK andXCER(A/B). This mode is used for symmetric transmitand receive operation.† DX is masked or driven to hi-Z during (a) interpacket intervals, (b) when a channel is masked regardless of whether it is enabled,or (c) when a channel is disabled.
42Using 2 partitions A and B McBSP channels are activated using an alternating scheme. After a sync pulse:Receiver or transmitter begins with the channels in partition A and alternates between part. B and A until the end of the frame.Assigning blocks to partitions. Any 2 of the 8 blocks can be assigned to A and B:Assign an even-numbered block to A by writing the 2 (R/X)PABLK bits and an odd-numbered block to B (R/X)PBBLK.The channels are controlled the receive or transmit channel enable registers (R/X)CERCA, (R/X)CERA.
43Using 2 partitions A and B Blocks can be reassigned during communication if we want to use more than 32 selected channels.It is not possible to modify the block assignment of a partition during its transfer.The block currently involved in the transmission is reflected in the (R/X)CBLK bits. They can be polled.At the end of a block, an interrupt can be sent to the CPU that checks (R/X)CBLK bits and updates the inactive partition.
44Using 8 Partitions RMCME/XMCME = 1 Partitions are activated in the order:A B C D E F G H.The (R/X)PABLK and (R/X)PBBLK are ignored.The blocks are assigned to the partitions in natural order:A: block 0, channels 0 to 15, reg. (R/X)CERAB: block 1, channels 16 to 31, reg. (R/X)CERB…H: block 7, chan. 112 to 127, reg. (R/X)CERH
45Receive Channels Disabled If a receive channel is disabled, any bits received in that channel are passed only as far as the receive buffer register(s) (RBR(s)).The receiver does not copy the content of the RBR(s) to the DRR(s), and as a result, does not set the receiver ready bit (RRDY).Therefore, no DMA synchronization event (REVT) is generated, and if the receiver interrupt mode depends on RRDY (RINTM = 00b), no interrupt is generated.
46Enabling/Disabling versus Masking/Unmasking For transmission, a channel may be:Enabled and unmaskedTransmission can begin and be completedEnabled: Data are passed from DXR to XSR.Unmasked: Data in XSR shifted out on DX pin.Enabled and maskedTransmission can begin but cannot be completedMasked: DX pin is held in high impedance. Avoids bus contention on a shared serial bus.DisabledTransmission cannot occur. No DXR to XSR copy.The bit XRDY is not set.
47Channel Enable Registers RCERx and XCERx In C5410 and C5420, there are 2 receive and 2 transmit Channel Enable Registers: RCERA, RCERB, XCERA, XCERB.In C5416 and C5510, there are 8 receive + 8 transmit Channel Enable Registers: RCERA to RCERH and XCERA to XCERH.RCERAXCERARCEA(0:15) Receive Channel Enable-RCEA n= 0 Disables reception of nth channel in an even-numbered block in partition ARCEA n= 1 Enables reception of nth channel in an even-numbered block in partition A
48SPI ModeThe SPI protocol is a master-slave configuration, with one master device and one or more slave devices. The interface consists of four signals.The clock stop mode of the McBSP provides compatibility with the SPI protocol.
49McBSP Pins as General Purpose I/O pins 1 of 2 Two conditions allow the serial port pins (CLKX, FSX, DX, CLKR, FSR and DR) to be used as general purpose input/output (I/O) rather than serial port pins:1) The related portion (transmitter or receiver) of the serial port is in reset; (R/X)RST = 0 in SPCR[1,2].2) General purpose I/O is enabled for the related portion of the serial port; (R/X)IOEN = 1 in the PCR.In the case of FS(R/X), FS(R/X)M=0(or 1) configures the pin as an input (or output).When configured as an output, the value driven on FS(R/X) is the value stored in FS(R/X)P.If configured as an input, FS(R/X)P becomes a read-only bit that reflects the status of that signal.
50McBSP Pins as General Purpose I/O pins 2 of 2 CLK(R/X)M and CLK(R/X)P work similarly for CLK(R/X).DX and DR as GPIO pins:the value of the DX_STAT bit in the PCR is driven onto DX.DR is always an input and its value is held in the DR_STAT bit in the PCR.CLKS as a general purpose input:both the transmitter and receiver must be in reset state and (R/X)IOEN = 1, because CLKS is always an input to the McBSP and affects both transmit and receive operations.
51McBSP Operation in Power-down Mode For the C5416, Power-down modes may be invoked in several ways:executing the IDLE instruction or driving the HOLD input low with the HM status bit set to one.The McBSP can take the CPU out of IDLE using a transmit or receive interrupt.When in IDLE1 or HOLD modes, the McBSP continues to operate normally with no restrictions.In IDLE2 or IDLE3 modes, the internal device clocks provided to the peripherals are stopped.If external clock and frame-sync are provided, the McBSP can continue to operate, and receive and transmit interrupts can be used to exit the IDLE state.If either clocks or frame-syncs are internal, the McBSP will stop in IDLE2/3.In IDLE2/3, the internal clocks to the McBSP and the DMA controller are started automatically when a transfer begins, and stopped after the transferis completed.
52McBSP Operation in Power-down Mode For the C5510, The McBSP is placed into its idle mode when:the PERIPH idle domain is idle (PERIS = 1 in ISTR)the McBSP idle enable bit is set (SPn = 1) in the PICR register. When the McBSP is in the Idle state, it is unable to receive or transmit data.In the McBSP idle mode:If the McBSP is operates with internal clocking and frame sync., it will be completely stopped.If the McBSP is operates with ext. clocking and frame sync., the external interface portion of the McBSP continues to function during external clock activity periods. The McBSP sends a request to activate the PERIPH and DMA idle domains when it needs to be serviced. If the domains were idle, they are made idle again after the McBSP has been serviced.
53Emulation FREE and SOFT Bits FREE and SOFT are special emulation bits that determine the state of the serial port clock when a breakpoint is encountered in the high-level language debugger.If the FREE bit is set to 1upon a software breakpoint, the clock continues to run (free runs) and data still shifts out. When FREE = 1, the SOFT bit is a don’t care.If the FREE bit is cleared to zero, then the SOFT bit takes effect.If the SOFT bit is cleared to zero, then the clock stops immediately, thus aborting a transmission.If the SOFT bit is set to one and a transmission is in progress, the transmission continues until completion of the transfer, and then the clock halts.The receiver-side functions in a similar fashion.
54Differences Between C5416 and C5510 McBSP Addressing of McBSP registers:C5416: sub-bank systemSome registers are mapped in data memory page 0: DRR, DXR + SPSA and SPSDSPSAx: McBSP Sub-Address register associated with a SPSD Sub-bank Data register containing the value for one of the sub-bank registersThe other registers are sub-bank registers accessed by sub-addresses relative to SPSA.C5510: Registers are mapped in the I/O spacePower-down modesC5416 McBSPRegisters addr.
55Configuration of the McBSP 1 of 3 Receiver/transmitter configurationPlace the McBSP receiver / transmitter in resetProgram the McBSP registers for the desired receiver / transmitter operationTake the receiver / transmitter out of reset
56Configuration of the McBSP 2 of 3 Global behaviorSet the receiver pins to operate as McBSP pinsEnable/disable the digital loopback modeEnable/disable the clock stop modeEnable/disable the receive multichannel selection modeData behaviorChoose 1 or 2 phases for the receive frameSet the receive word length(s)Set the receive frame lengthEnable/disable the receive frame-sync ignore functionSet the receive companding modeSet the receive data delaySet the receive sign-extension and justification modeSet the receive interrupt mode
57Configuration of the McBSP 3 of 3 Frame-sync behaviorSet the receive frame-sync modeSet the receive frame-sync polaritySet the SRG frame-sync period and pulse widthClock behaviorSet the receive clock modeSet the receive clock polaritySet the SRG clock divide-down valueSet the SRG clock synchronization modeSet the SRG clock mode [choose an input clock]Set the SRG input clock polarity
58Configuration of the McBSP with CSL Example of the DSK-CCS tutorial audioIO.c of Chapter 4 for the ‘C5416.First we examine the file audioIOcfg_c.c that configures the DSP,Then we explain how to automatically generate it with the GUI interface of CCS.Parameters:The McBSP 2 is usedSingle phase mode32 bits words.List of files of the example to examineaudioIOcfg.haudioIOcfg_c.c
59File audioIOcfg.h Includes the Chip Support Library for the McBSP Defines variables
60Example of McBSP configuration file 1st part of the file audioIOcfg_c Example of McBSP configuration file 1st part of the file audioIOcfg_c.cSPCR1=0, SPCR2=0x200RCR1=0x00a0, RCR2=0XCR1=0x00a0, XCR2=0SRGR1=0x1f00, SRGR2=0x003fMCR1=0x0000, MCR2=0x0000PCR=0x0083All receive channel enable registers RCERx are set to 0
61Example of McBSP Configuration File Last Part of the File All transmit channel enable registers XCERx are set to 0Using CSL to open and initialise the McBSP 2.
62File audioIOcfg_c.c 1 of 3SPCR1 = 0, SPCR2 = 0x0200, Serial Port Control RegistersRJUST=0, CLKSTP=0, DXENA=0, RINTM=0, RSYNCERR=0, RRST=0FREE=1, SOFT=0, FRST=GRST=XINTM=XSYNCERR,XRST=0RCR1 = 0x00A0, RCR2 = 0, Receive Control RegistersRWDLEN1=101 = 32 bits words, RFLEN1=0 = 1 word per frameRDATDLY=0, 0 bit data delayRFIG=0, received frame-sync not ignoredRCOMPAND=0, no compandingRWLEN2=0RFRLEN2= 0RPHASE = 0 = 1 phase per frame, RWLEN2 and RFRLEN2 ignored.XCR1 = 0x00A0, XCR2 =0 same remarks as for RCR, Transmit Control Register.
63File audioIOcfg_c.c 2 of 3SRGR1 = 0x1F00, SRGR2 = 0x003F, Sample Rate Generator RegistersCLKGDV =0, divide down value for CLKGFWID = 0x1F=31, frame-sync pulse width for FSG = 32 CLKG cyclesFPER=0x3F=63, Frame-sync period bits for FSG, the period between frame-sync pulses on FSG is 64 CLKG cycles.FSGM=0, if FSXM=1 in PCR, the McBSP generates a frame-sync pulse when DXR is copied in XSR. But here FSXM=0 (see PCR).CLKSM=0, the input clock for SRGR is taken on CLKS pin or CLKR pin depending on SCLKME bit in PCR. Here SCLKME=1=signal on CLKR.CLKSP=0, CLKS pin polarity, the rising edge on CLKS pin drives the clock signal CLKG and FSG.GSYNC=0, no clock synchronizationMCR1 = 0, MCR2 = 0, no multichannel selection, Multichannel Control Registers
64File audioIOcfg_c.c 3 of 3 PCR = 0x0083, Pin control Register CLKRP=1, CLKXP=1, clock polarityAs CLKRM=0, CLKR is an input and the received data is sampled on the rising edge of CLKR.transmit data is driven on falling edge of CLKX.FSRP=FSXP=0, frame-sync pulses are active high.DRSTAT=0, DXSTAT=0, not applicable here.CLKSTAT=0,not applicable here.SCLKME=1, SRGR input clock is taken from CLKR pin (CLKSM=0).CLKRM=CLKXM=0, not in DLB so the CLKR and CLKX pins are inputs that suppies the internal clocks.FSRM=FSXM=0, Receive and transmit frame-sync is supplied by an ext source via FSR and FSX pins.RIOEN=XIOEN=0, the McBSP pins are not GPIO pinsIDLEEN=0, the McBSP remains active when the PERIPH domain is idled.RCERx and XCREx = 0, There is no multichannel selection
65Example using the ‘C5416 DSK 1 of 2 Create a new project iomcbsp.pjt and Create a new cdb file
66Example using the ‘C5416 DSK 2 of 2 Save (File>Save) the new configuration file under the project directory: iomcbsp.cdbAdd to the project two of the files generated at the previous step: the configuration file (*.cdb) and the linker command file (*.cmd).Copy the file audioIO.c of chapter ‘ example in the project directory and rename it iomcbsp.cModify the main source file: iomcbsp to include the header file iomcbspcfg.h generated at the configuration stepand add iomcbsp.c to the project.Modify build options:Project>Build Options to add the dsk5416f.lib library and set use far calls.
67Configuring the McBSP using the McBSP Configuration Manager of the CSL GUI
71Configuring the McBSP using the CSL GUI 4 of 4 Modify:« Receive Lengths », « Transmit Lengths » to set word length to 32 bits« Sample_Rate Gen »,choose generator clock source=BCLKRset frame width to 32 and frame period to 64.« Transmit Mode », clock polarity = falling edge« General »Set Breakpoint Emulation to do not stop to set FREE = 1.Save the new iomcbsp.cdb file and look at the iomcbspcfg_c.c file. It should be quite similar to the audioIOcfg_c.c file for the initialization part.
73Configuring the McBSP using the Resource Manager of the CSL GUI Use the McBSP Resource Manager menu to generate the MCBSP_open()and the MCBSP_config() CSL functions.It allows to select, open, initialize a deviceWe select McBSP 2We ask for the McBSP handle creation with the name C54XX_DMA_MCBSP that will be used by the routines of the BSL.And we ask for the opening of the McBSP handle and for the pre-initialization with object mcbspCfg0.
77Configuring the McBSP using the CSL GUI 4 of 4 Save the file iomcbsp.cdbOpen the file iomcbspcfg_c.cYou should see the instructions for the opening and initialization of the McBSP.
78Final version of the iomcbspcfg_c.c File Creation of the McBSP handleOpening and initialization of McBSP2
79Test the iomcbsp program Build the projectLoad iomcbsp.out in Program memoryCheck the programusing a microphone (or a CD output) and earphones, you should hear the input (mike or CD) in the earphones (or loudspeaker).Use tools>C54xx McBSP to view all the registers of the McBSP.
80References User’s guides Spru302: Tms320c5416.pdf Spru592a: TMS320C54x DSP Reference Set Volume 5: Enhanced Peripherals.Tms320c5416.pdfSpru592a:TMS320VC5501/5502/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide.