Presentation on theme: "Chapter 11 Understanding and Programming the Bootloader"— Presentation transcript:
1Chapter 11 Understanding and Programming the Bootloader DSP C5000Chapter 11Understanding and Programming the Bootloader
2BOOT Loader General Features RAMEPROM/FlashslowDSPRAMfastBootloader is used to transfer code from an external source into internal or external program memory following power-up.Code can be stored in slow non-volatile memory, and be transferred to high-speed memory to be executed.
4At Reset: How Does the DSP Boot? Execution begins at location FF80h of the on-chip ROM if the MP/MC pin is low, external ROM otherwise.At FF80h a branch instruction jumps to the bootloader programIt sets up the CPU status registers before initiating the bootload.Interrupts are globally disabled and internal RAMs are mapped into program/data space (OVLY = 1).All program and data accesses are done with 7 Wait States.The size of the external memory bank is set to 4K words.The bootloader is factory-programmed in ROM.
5BOOT Mode SelectionThe bootloader reads the I/O port address 0FFFFh by driving the I/O strobe signal low.The lower eight bits of the word read from I/O port address 0FFFFh specify the mode of transfer.The boot routine selection (BRS) word determines the boot mode.
6Boot Routine Selection Modes The host port interface (HPI) uses interrupt 2 for bootload (INT2). If INT2 is not latched, the boot routine skips HPI boot mode.The lower eight bits from the I/O address, 0FFFFh determine the boot mode:Parallel EPROM Boot, BRS word determines the 8- or 16-bit parallel EPROMSerial boot Mode, the six least significant bits and the configuration of CLKX and FSX pins determine whether to use the 8- or 16-bit bootload serial boot option.BRS word also determines the 8- or 16-bit parallel I/O mode.
7HPI Boot loadingHPI is an 8 or 16-bit parallel port that interfaces a host processor to the C54xThe host interrupts the DSP by writing to the HPI control register (HPIC).The DSP interrupts the host by asserting the host interrupt (HINT) signal.If HINT=0 then the HPI boot mode is selected.This signal is tied to the external interrupt INT2 input pin if HPI boot mode is selected.If HPI boot mode is selected, the host must download the code to on-chip HPI RAM before the HPI brings the device out of reset. The code will execute from address 1000h .The host controller must clear HINT by writing to HPIC.
816-Bit/8-Bit Parallel Boot If the code is stored in EPROMs (8 or 16 bits wide) parallel boot option is used.The code is transferred from data to program memory.The 6 MSBs of the source address are specified by the SRC field of the BRS wordIf 16-bit parallel mode is selected, data is read in 16-bit words from the source address with auto-incremented .The destination address and the length of the code are specified by the first two 16-bit words.After the code is transferred to program memory, the C54 branches to the destination address.
98-bits EPROM Parallel Boot 2 Memory locations are read to make the 16-bit wordof program memory
11I/O BootIn I/O boot mode, asynchronous transfer of code is done from I/O address 0h to internal/external program memory.Word can be 16 or 8 bits long.The DSP communicates with external devices using the BIO and XF handshake protocol
13Serial Boot Mode Serial boot can be done using McBSP or TDM Eight modes are available for the serial boot optionTransfer can be done on 8 or 16 bits words
14Warm Boot If the warm boot option is specified: the C54x transfers control to the entry addressThe warm boot option can be used after a warm device reset or if the program has already been transferred to internal or external memory (DMA).The six MSBs of the entry code are specified by the SRC or ADDR fields of the BRS word.See Warmboot program exampleProgramme link
15Programming the Bootloader Application for the C54x: Determine vector table and visual linker inputsWrite fir_ISR and application setup codeUse HEX500 to create a boot table, discuss bootload options
16[Project] - Physical Memory, Vector Table The following sections are booted: - coefficients - code - vectorsBootloader moves code from Data space to Program Space. Bootloader sets OVLY bit to one.Using VL, create load/run maps for coeffs, code and vectors. VL will resolve the run-time symbolsVectors.ASMINBUF: start = 00080h, end = 000DFhCODE: start = 00100h, end = 004FFhVECS: start = 00500h, end = 005FFhOUTBUF: start = 02000h, end = 0205FhCOEFF: start = 02060h, end = 0225FhDARAM2: start = 03000h, end = 03FFFhFLASH: start = 0E000h, end = 0EFFFhRAM (run)Flash (load)CODEcodevecscoeffsbootVECS;unused: RETE;Ch2DMAC2:B fir_isrCOEFFSLet’s now review ALL of the code...
17Project.ASM ;** .set statements ** .mmregs DMPREC .set 54h ;Channel Priority and Enable ControlDMSA .set 55h ;DMA sub-addressDMSDI .set 56h ;DMA write without indexingDMSDN .set 57h ;DMA write with indexingSPSA0 .set 38h ;McBSP0 sub-addressSP0 .set 039h ;Write for McBSP0 sub-addressed regsDRR10 .set 21h ;Data Receive for McBSP0DXR10 .set 23h ;Data Transmit for McBSP0SWCR .set 2bh ;Software Wait State;** allocate aligned circular buffers for input and output **x .usect "in_bufs",96bos .usect "STK",128FLAG1 .usect "vars",3 ;signal first time thru input routineFLAG2 .set FLAG ;signal first time thru output routineCOUNT .set FLAG1+2 ;which buffer is being processed? 1,2,3y .usect "out_bufs",96;** allocate 16 initialized coeffs of 1/16th each **.sect "coeffs"a .int 800h,800h,800h,800h.int 800h,800h,800h,800h
21;** McBSP0 (rcv) out of reset ** STM #00h,SPSA0 ;SPCR10STM #4001h,SP0;** AIC out of reset **CALL XSR_EMPTYSSBX XFSTM #0181h,DXR10 ;CR-1RSBX XF;** enable DMA Ch2 interrupt, Clear IFR **STM #0400h,IMR ;DMA-INT CH2STM #0FFFFh,IFR ;Clr IFR;** fir_isr setup code **LD #FLAG1,DP ;FLAG1,FLAG2 and COUNT on same DPST #0,FLAG1 ;assure FLAG1 (for in_bufs) is zeroST #0,FLAG2 ;assure FLAG2 (for out_bufs) is zeroST #0,COUNT ;assure COUNT is zeroSTM #31,BRC ;generate 32 resultsSTM #96,BK ;Moe, Larry, Curly input and;Tom, Dick, Harry output buffersSTM #1,AR0 ;emulate post inc by 1STM #0Fh,DMSA ;0Fh is DMSRC3 (for all DMSRC3 writes)RSBX OVM ;clear overflow modeSSBX FRCT ;set fractional modeSSBX SXM ;set sign extensionRSBX INTM ;enable global interrupts last
22;************************* ;** Main Loop **main:IDLE 1 ;When DMA2 interrupts main, fir_isr runs andNOP ;execution returns to this code. We then goNOP ;back into IDLE mode and wait for theNOP ;next interrupt.NOPB main;** XSR Empty Test **XSR_EMPTY:LD #0,DPBITF @SP0,2h ;poll XEMPTYn flagBC XSR_EMPTY,TCRET
23;**************** FIR ISR (DMA Ch2 Int) **************** LD #FLAG1,DP ;Ignore First DMA Interrupt;ST ;BC done,NTC ;ADDM ;COUNT holds 1,2,3 for Moe,Larry,Curly;1st pass (Moe)?BC loopinit,TC ;if so, setup ARs and set output SRC;2nd pass (Larry)?BC test3,NTC ;NO, go to test3STM #y+32,DMSDN ;DMA3 SRC = out_buf #2B mathtest3: ;3rd pass (Curly)?BC fourth,NTC ;NO, must be fourth, reset counterSTM #y+64,DMSDN ;DMA3 SRC = out_buf #3fourth: ST #1,COUNT ;reset COUNT, reload ARs as 1st passloopinit:STM #x,AR3 ;setup ARs for MACSTM #y,AR4STM #y,DMSDN ;DMA3 SRC = out_buf #1math: ;...
24math: STM #a,AR2 ;always re-init coeff pointer RPTB tstflg2-1MPY *AR2+,*AR3+0%,A ;1st product, AR3 circles on 96RPT # ;mult/acc 15 termsMAC *AR2+,*AR3+0%,AMAR *+AR3(-15)% ;modify AR3 by -15 circularlySTH A,*AR4+ ;store resulttstflg2:;Write dummy DXR to initiateST ;first DMA3 transfer IF the FIRSTXC 2,NTC ;out_buf is readySTM #0,DXR10done: RETE ;return with enableNow that we’ve written all of the code, how does it get loaded into the system?
25C5402 bootloader can copy to extended program space C5402 Boot Loader - OptionsBoot Mode Description TriggerNo Boot MP/MC=1, begin vector NoneHPI DSP waits, host xfers code to mem. PC = *07Fh. INT2n lowParallel Boot Loader xfrs code. Src = 8/16-bit async mem FFFFh in I/O = src dest = int/ext’l RAM. PC = entry point specified. src = 8AA or 10AAh then tries Data for srcI/O Boot Loader transfers code via I/O addr 0h. Drives XF high then Handshake via XF/BIO. waits for BIO responseSerial Boot Loader configures SP and reads 1st word 8AA or 10AAh rcvd? McBSP0 - 16bit , McBSP1 - 8bit.Serial Bootloader configures SP in SPI-mode. INT3n low EEPROM McBSP1 onlyEach C54x device has specific options and modes. Refer to the boot-loader specification for your chosen device for more details.C5402 bootloader can copy to extended program space
26[Project] - Parallel Boot When I/O space is accessed, SRCaddr=F000h is returnedBoot table Generated by HEX500F000h10AA ;parallel bootFFFFhF000h0900h ;SWWSR0000h ;SWCRIS0000h ;BSCROEn1D15.D8D7D00000h ;XPC entry pointFstart ;PC entry pointSize of 1st section0000h ;XPC DEST0100h ;PC DEST - CODECode word 1-N - (CODE)Size of 2nd section0000h ;XPC DEST0500h ;PC DEST - VECSCode word 1-N - (VECS)Transparent Buffer… (COEFFS)
27END 'C55x [Project] - Using HEX500 HEX500 firmware.cmd project.out /* input file */-e start /* set entry (execution) point */-i /* select Intel format */-map project.mxp /* map file for HEX500 */-o project.hex /* output file */-memwidth 16 /* DSP accesses mem as 8/16-bit */-romwidth 16 /* physical mem width, 8/16-bit */-boot /* make all sections bootable */-bootorg 0xF000 /* location of boot table */Must assemble .OUT file using -v548 if using C548/9 and C54x devicesProgramming formats: 16-bit ASCII hex, Tektronix, Intel MCS-86, Motorola S (16/24/32-bit addresses), 16-bit TI-Tag'C55xENDFlash burn programme
28Different boot modes of the C55x: C55x Boot LoaderDifferent boot modes of the C55x:Boot from the Enhanced Host Port Interface (EHPI)The code to be executed is loaded into on-chip memory by an external host via the EHPI.Parallel EMIF boot from 8-, 16- or 32-bit external asynchronous memoryThe bootloader reads the boot table from EMIF configured for asynchronous memory. The boot table contains the code or data sections to be loaded, the destination addresses for each of the sections, the execution address.
29Different Boot Modes of the C55x Standard serial boot through McBSP0 (8- or 16-bit supported)The bootloader receives the boot table from the McBSP0 operating in standard mode and loads the code according to the information specified in the boot table.SPI EEPROM serial boot through McBSP0Same as standard serial except that data can be received from an SPI-format serial EEPROM, or from another SPI-compliant serial port operating as a SPI slave.
30More Boot Loader Features Boot mode selection is I/O pin-controlledFirst address of execution after the boot load is complete is programmable and is stored in the boot table.Port-addressed register configuration during bootSome of the port-addressed registers used to control peripherals can be modified during the bootload, providing the ability to modify the clock generator, reconfigure the EMIF strobe timings or preset peripheral register values.Programmable delays of up to CPU clock cycles can be added during the register configuration process to ensure that new configurations are complete before the boot process continues.
31On Chip standard ROM Description On-chip ROM contains several factory-programmed sections including:
32Bootloader Resource Initialisation Data Stack register (SP) is initialised to address h, and the System Stack register (SSP) to address h.The stack configuration is set to 32-bit with slow return.The INTM bit of Status Register 1 (ST1_55) is set to 1, to disable interrupts.Two words are reserved for temporary storage of the entry-point address at h and h.SXMD bit of ST1-55 is cleared , to disable sign extension mode. After the bootloader copies all of the sections, SXMD is set back to 1 before execution is transferred to the application.The 54CM bit of ST1-55 is set to 1, to enable C54x compatibility mode during and after the bootload.
33Boot Loader Mode Selection BOOTM pins (sampled at reset, stable for 30 cycles) determine type of boot:Boot up to 64Kx16 of the C5510’s internal memoryBoot performed by ROM-coded boot routines during resetBOOTM[3:0]No boot (begin execution at reset vector)EHPIExternalSerial5510ROMBoot LoaderThe external pins - BOOTM[2:0] - drive the boot load sequence. 3 bits selects 8 options (none, external: 16/32-bit, EHPI, serial: 8, 16-bit - 6 options, two are reserved).The size is limited to 64K WORDS because you can only specify a 16 bits size, which is in words. Also, the destination address for the external and serial boot is specified in two 16-bit locations (as shown on the next slide), but only the appropriate # of bits are used to specify the lower memory locations in internal memory. This allows the user to specify the MDP as well as the lower 16 bits in the DEST address.If you desire to boot into external memory or more than 64K words, simply boot a small boot-load routine which sets up the DMA to copy from anywhere to anywhere you like.
34BOOT Mode Selection 0000 No boot BOOTM BOOT Mode0000 No boot0001 Serial EEPROM (SPI) boot from McBSP0 supporting 24-bit addressNo boot1001 Serial EEPROM (SPI) boot from McBSP0 supporting 16-bit addressParallel EMIF boot from 8-bit external asynchronous memoryParallel EMIF boot from 16-bit external asynchronous memory1100 Parallel EMIF boot from 32-bit external asynchronous memory1101 EHPI1110 Standard serial boot from McBSP0 (16-bit)1111 Standard serial boot from McBSP0 (8-bit)
35Boot Load Options EHPI External Serial uP SARAM 8000Host uP boots SARAM during DSP resetAfter boot: execution begins at address 8000h (word)EHPI16- or 32-bit async, CE1CE1: 20_0000h (word)Multiple sections can be bootedafter boot: execution begins at DEST of 1st sectionInternalCE1sizeDESTcodeExternal...0000h8- or 16-bit transfersBootloader configures: external CLK and FS, frmlen=1Multiple sections can be bootedAfter boot: execution begins at DEST of 1st sectionMcBSP0InternalDESTcodeSerialsize...0000hThe external pins - BOOTM[2:0] - drive the boot load sequence. 3 bits selects 8 options (none, external: 16/32-bit, EHPI, serial: 8, 16-bit - 6 options, two are reserved).The size is limited to 64K WORDS because you can only specify a 16 bits size, which is in words. Also, the destination address for the external and serial boot is specified in two 16-bit locations (as shown on the next slide), but only the appropriate # of bits are used to specify the lower memory locations in internal memory. This allows the user to specify the MDP as well as the lower 16 bits in the DEST address.If you desire to boot into external memory or more than 64K words, simply boot a small boot-load routine which sets up the DMA to copy from anywhere to anywhere you like.On the external boot, 0000h terminates the boot.Encourage the students to look up the header information if they plan to use the bootloader in external or serial mode.size: #words, DEST: word addr, 0000h terminates boot