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University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 1 Computer Systems the impact of caches.

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Presentation on theme: "University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 1 Computer Systems the impact of caches."— Presentation transcript:

1 University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 1 Computer Systems the impact of caches

2 University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 2 Introduction Different sorts of memory On-die 0/1/10 cycles On-board 100 On-disk Off-machine

3 University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 3 The CPU-Memory Gap The increasing gap between disk, DRAM and SRAM, CPU speeds.

4 University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 4 Storage Trends bigger, not faster (Culled from back issues of Byte and PC Magazine) metric :1980 $/MB8, ,000 access (ns) typical size (MB) ,000 DRAM metric :1980 $/MB ,000 access (ms) typical size (MB) ,0009,0009,000 Disk

5 University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 5 metric :1980 $/MB19,2002, access (ns) typical size (MB) Processor trends faster :1980 processor PentP-III clock rate (MHz) cycle time (ns)1, SRAM

6 University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 6 Intel Processors Cache SRAM L1L K- Pentium19938 K - Pentium Pro K 256K-1M Pentium II K 512K ½ Celeron A K 128K Pentium III Coppermine K 256K Pentium 4 Willamette K8 K256K Pentium 4 Northwood K8 K512K

7 University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 7 Memory Hierarchy Registers On-chip L1 cache (SRAM) Main memory (DRAM) Local secondary storage (local disks) Larger, slower, and cheaper (per byte) storage devices Remote secondary storage (distributed file systems, Web servers) Local disks hold files retrieved from disks on remote network servers. Main memory holds disk blocks retrieved from local disks. Off-chip L2 cache (SRAM) L1 cache holds cache lines retrieved from the L2 cache. CPU registers hold words retrieved from cache memory. L2 cache holds cache lines retrieved from memory. L0: L1: L2: L3: L4: L5: Smaller, faster, and costlier (per byte) storage devices

8 University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 8 Pay the price To access large amounts of data in a cost-effective manner, the bulk of the data must be stored on disk 1GB: ~$ GB: ~$110 4 MB: ~$500 Disk DRAMSRAM

9 University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 9 Locality Principle of Locality: –Programs tend to reuse data and instructions near those they have used recently, or that were recently referenced themselves. –Temporal locality: Recently referenced items are likely to be referenced in the near future. –Spatial locality: Items with nearby addresses tend to be referenced close together in time.

10 University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 10

11 University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 11 Locality Example Data –Reference array elements in succession (stride-1 reference pattern): –Reference sum each iteration: Instructions –Reference instructions in sequence: –Cycle through loop repeatedly: sum = 0; for (i = 0; i < n; i++) sum += a[i]; return sum; Spatial locality Temporal locality

12 University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 12 Power Programmer Claim: Being able to look at code and get a qualitative sense of its locality is a key skill for a professional programmer. Good locality? int sumarrayrows(int a[M][N]) { int i, j, sum = 0; for (i = 0; i < M; i++) for (j = 0; j < N; j++) sum += a[i][j]; return sum }

13 University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 13 Stride-M example Question: Does this function have good locality? int sumarraycols(int a[M][N]) { int i, j, sum = 0; for (j = 0; j < N; j++) for (i = 0; i < M; i++) sum += a[i][j]; return sum }

14 University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 14 Matrix M=2,N=3 Adress Contentsa 00 a 01 a 02 a 10 a 11 a 12 Acces order Adress Contentsa 00 a 01 a 02 a 10 a 11 a 12 Acces order int sumarrowrows() int sumarrowcols()

15 University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 15 Expect: Stride-1 is better! –int A[2][4]

16 University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 16 Reality: small matrices fit in cache –int A[32][32]

17 University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 17 Reality: Performance-drop cache L2 / L1 not dramatic –int A[180][180]

18 University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 18 Reality: Only when DRAM is accessed, the penalty can be seen –int A[512][512]

19 University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 19 Memory Mountain

20 University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 20 Summary As long as your data fits in the cache, and your program shows good locality, good performance is guaranteed.

21 University of Amsterdam Computer Systems – the impact of caches Arnoud Visser 21 Assignment Practice Problem 6.9 (p. 624): 'Order three functions to the spatial locality enjoyed by each.' Practice Problem 6.22 (p. 659): 'Estimate the time, in CPU cycles, to read a 8-byte word, from the different L1-d of a i7 processor


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