Presentation is loading. Please wait.

Presentation is loading. Please wait.

HM-ES-th1 Les 7 Hardware/Software Codesign with SystemC.

Similar presentations


Presentation on theme: "HM-ES-th1 Les 7 Hardware/Software Codesign with SystemC."— Presentation transcript:

1 HM-ES-th1 Les 7 Hardware/Software Codesign with SystemC

2 24 Als voorbeeld bekijken we een Single-Purpose Processor die de Greatest Common Divider uitrekent. We beginnen met een functional level SystemC model waarin het algoritme wordt beschreven. Van Algoritme naar RTL gcd x_i y_i r_o

3 25 SystemC Untimed Model Euclid's algorithm 300 BC template SC_MODULE(gcd) { sc_in x_i, y_i; sc_out r_o; SC_CTOR(gcd) { SC_METHOD(run); sensitive << x_i << y_i; } private: void run() { T x = x_i.read(); T y = y_i.read(); while (x != y) { if (x > y) { x -= y; } else { y -= x; } r_o.write(x); } };

4 26 SystemC Test Bench gcd x_i y_i r_0 tb_gcd x_oy_o r_i template SC_MODULE(tb_gcd) { sc_in r_i; sc_out x_o, y_o; SC_CTOR(tb_gcd) { SC_THREAD(run); } private: void check(const T& x, const T& y, const T& r) { wait(10, SC_NS); x_o.write(x); y_o.write(y); wait(10, SC_NS); assert(r_i.read() == r); } void run() { check(0, 0, 0); check(234, 96, 6); check(12345, 67891, 1); check(12345, 67890, 15); check(12345, 12345, 12345); wait(10, SC_NS); x_o.write(0); y_o.write(0); sc_stop(); //...

5 27 SystemC sc_main Nu kunnen we timing informatie aan het model toevoegen om te kijken of dit algoritme aan de timing eisen voldoet. int sc_main(int argc, char *argv[]) { gcd gcd("gcd"); tb_gcd tb_gcd("tb_gcd"); sc_buffer x, y, r; gcd.x_i(x); gcd.y_i(y); gcd.r_o(r); tb_gcd.x_o(x); tb_gcd.y_o(y); tb_gcd.r_i(r); sc_start(); return 0; }

6 template SC_MODULE(gcd) { // idem void run() { while(1) { wait(); T x = x_i.read(); T y = y_i.read(); wait(10, SC_NS); while (x != y) { if (x > y) { x -= y; } else { y -= x; } wait(10, SC_NS); } r_o.write(x); } }; 28 SystemC approximately-timed Voeg wait(…, SC_NS) statements toe!

7 29 SystemC approximately-timed template SC_MODULE(tb_gcd) { // idem void check(const T& x, const T& y, const T& r) { auto start_time_stamp = sc_time_stamp(); x_o.write(x); y_o.write(y); wait(); wait(10, SC_NS); assert(r_i.read() == r); auto end_time_stamp = sc_time_stamp(); cout << " << sc_time_stamp() << ": gcd(" << x << "," << y << ") = " << r << " duration: " << end_time_stamp - start_time_stamp << endl; }

8 30 Stel dat dit voldoet aan de timing specificaties. We maken nu een nauwkeuriger model door het clock signaal clk toe te voegen. We voegen meteen een go_i en done_o handshake signaal toe. Waarom? SystemC cycle accurate gcd go_ix_i y_i done_or_o clk

9 31 SystemC cycle accurate done_o x_i y_i go_i r_o gcd go_ix_i y_i done_or_o clk template SC_MODULE(gcd) { sc_in_clk clk; sc_in go_i; sc_in x_i, y_i; sc_out done_o; sc_out r_o; SC_CTOR(gcd) { SC_THREAD(run); sensitive << clk.pos();

10 32 SystemC cycle accurate void run() { wait(); while(1) { do { wait(); } while (!go_i.read()); T x = x_i.read(); T y = y_i.read(); wait(); while (go_i.read() && x != y) { if (x > y) { x -= y; } else { y -= x; } wait(); } if (go_i.read()) { r_o.write(x); done_o.write(true); } do { wait(); } while (go_i.read()); done_o.write(false); }

11 33 SystemC cycle accurate template SC_MODULE(tb_gcd) { sc_in done_i; sc_in r_i; sc_out go_o; sc_out x_o, y_o; SC_CTOR(tb_gcd) { SC_THREAD(run); sensitive << done_i; } private: void check(const T& x, const T& y, const T& r) { auto start_time_stamp = sc_time_stamp(); x_o.write(x); y_o.write(y); go_o.write(true); wait(); assert(r_i.read() == r); auto end_time_stamp = sc_time_stamp(); cout << " << sc_time_stamp() << ": gcd(" << x << "," << y << ") = " << r << " duration: " << end_time_stamp - start_time_stamp << endl; go_o.write(false); wait();

12 34 SystemC RTL Ga ervan uit dat de benodigde RTL componenten beschikbaar zijn (zie hand-outs). Ontwerp en implementeer Datapath en Controller.

13 35 Combinational components

14 36 Sequential components

15 37 single-purpose processor basic model controller and datapath controllerdatapath … … external control inputs external control outputs … external data inputs … external data outputs datapath control inputs datapath control outputs … … a view inside the controller and datapath controllerdatapath … … state register next-state and control logic registers functional units


Download ppt "HM-ES-th1 Les 7 Hardware/Software Codesign with SystemC."

Similar presentations


Ads by Google