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Professur für Technische Informatik A Self Distributing Virtual Machine for FPGA Multicores Klaus Waldschmidt J. W. Goethe-University Technische Informatik.

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Presentation on theme: "Professur für Technische Informatik A Self Distributing Virtual Machine for FPGA Multicores Klaus Waldschmidt J. W. Goethe-University Technische Informatik."— Presentation transcript:

1 Professur für Technische Informatik A Self Distributing Virtual Machine for FPGA Multicores Klaus Waldschmidt J. W. Goethe-University Technische Informatik Frankfurt/Main, Germany Dagstuhl April 2008

2 Professur für Technische Informatik a Slide 2 Klaus Waldschmidt – Dagstuhl April 08 One or more processors support the intelligence which is necessary for the smart behaviour. Things that think Things that think, a definition originally presented by MIT. Internet of things Embedded systems are more a or less networked systems. In consequence an Internet of things exists additionally to the wellknow Internet of information

3 Professur für Technische Informatik a Slide 3 Klaus Waldschmidt – Dagstuhl April 08 Embedded systems and System-on-chips Modern System-on-chips become more and more complex Time to market becomes more and more a necessity Robustness and trust in electronic systems is a big challenge in future Power reduction for mobile applications become more and more important A parallel, flexible, scalable, and generic architecture will be required in future. System-specification Hardware synthesis Communication synthesis Software- compilation Hardware/Software- partitioning Environment Reconfigurable system InputOutput ObserverController

4 Professur für Technische Informatik a Slide 4 Klaus Waldschmidt – Dagstuhl April 08 FPGA ObserverController FPGA software model Environment InOut Environment Reconfigurable system InputOutput ObserverController

5 Professur für Technische Informatik a Slide 5 Klaus Waldschmidt – Dagstuhl April 08 Multi-core FPGA (MP-SoC) Multi-core FPGAs create a new kind of system realization… …but there are still a lot of problems to solve: Power Manage- ment Reliability Perform- ance Flexibility Reliability, Flexibility and Power- Management Performance: Algorithms and programming (software) model Reliability: Increase of lifespan and robustness Flexibility for adaptivity and self-organization Power management: Energy reduction for mobility

6 Professur für Technische Informatik a Slide 6 Klaus Waldschmidt – Dagstuhl April 08 Autonomous and organic behaviour of multi-core computing systems parallel computing reconfigurable (dynamic) computing adaptive computing self- organization

7 Professur für Technische Informatik a Slide 7 Klaus Waldschmidt – Dagstuhl April 08 Multi-core Systems based on FPGA fxfx f1f1 f2f2 fyfy Processing element (PE) Custom HW function FPGA unite several PEs to form a parallel system increase number of PEs if needed use available space on the FPGA implement special functionality on the FPGA reconfigure at runtime M PR M PR M PR M PR M PR M PR M PR M PR M PR M PR M PR M PR M PR M PR M PR M PR What we need is a software model for FPGAs to make these features manageable. FPGA M PR M PR fyfy M PR f3f3 M PR M PR

8 Professur für Technische Informatik a Slide 8 Klaus Waldschmidt – Dagstuhl April 08 FPGA layer The Self Distributing Virtual Machine (SDVM) application Core type ACore type B The SDVM as a middleware between application and hardware ? application SDVM layer Application runs transparently distributed on several sites application site Application to be run on heterogeneous, distributed hardware Network on chip (NoC) (bus, mesh, crossbar, Clos Net, …) The SDVM is a virtualization of a parallel, adaptive, and heterogeneous cluster. ?? Sites can join and leave the cluster without disturbing the execution SDVM Sites can join … M PR M PR HW type X fyfy

9 Professur für Technische Informatik a Slide 9 Klaus Waldschmidt – Dagstuhl April 08 FPGA SDVM uses the dataflow principle to automatically distribute applications and data code is needed at execution time only and thus the params are moved separatelySDVM features (virtual) global shared memory using COMA principle SDVM features distributed dynamic scheduling (work stealing principle) sites may vanish (data is pushed out before) or join (new sites automatically ask for work) at runtime NoC (bus, mesh, crossbar, Clos Net, …) Working principle of the SDVM code fragments can be dynamically subsituted by configware memory processor reconf hardware site memory processor reconf hardware site memory processor reconf hardware site code params execute … params code params code params execute … config ware shutdown! code

10 Professur für Technische Informatik a Slide 10 Klaus Waldschmidt – Dagstuhl April 08 System-Virtualization using the SDVM 1. FPGAs allow for parallel systems: multiple hardcores multiple softcores multiple custom function units 2. FPGAs allow for heterogeneous systems: PowerPC hardcore MicroBlaze softcore custom function units 3. Runtime-reconfigurable FPGAs make dynamic systems possible. M PR M PR M PR M PR M PR M PR M PR M PR M PR M PR M PR M PR f1f1 f2f2 The adapted SDVM R will act as a virtual layer for dynamic reconfigurable Multi-Core FPGAs. FPGA Application NoC Core type A M PR Core type B M PR SDVMSDVM R

11 Professur für Technische Informatik a Slide 11 Klaus Waldschmidt – Dagstuhl April 08 SDVM R Objectives 1.Combine all PEs on the FPGA to create a parallel system. 2.Provide task mobility between all PEs even if they are heterogeneous. 3.Virtualize the I/O-system to enable the execution of a task on an arbitrary PE. 4.Combine the distributed memory of each PE to form a virtually shared memory. 5.Manage the reconfiguration of the FPGA. 6.Adjust the number of active PEs at runtime. 7.Hide the actual number of PEs from the application to ease programming. 8.Provide dynamic scheduling as well as code and data distribution. These features will be provided by the SDVM R software layer.

12 Professur für Technische Informatik a Slide 12 Klaus Waldschmidt – Dagstuhl April 08 FPGA Implementation architecture SDVM R site NoC SDVM R site The SDVM R is implemented as software running on each core. Each core forms an independent site of the SDVM R cluster. Custom function units will get attached to a core. Custom function units as independent sites are planned. (bus, mesh, crossbar, Clos Net, …) M PR PowerPC Hardcore M PR MicroBlaze Softcore SDVM R site M PR MicroBlaze Softcore fyfy custom function unit SDVM R site fyfy custom function unit

13 Professur für Technische Informatik a Slide 13 Klaus Waldschmidt – Dagstuhl April 08 Partial reconfiguration FPGA SDVM R site NoC (bus, mesh, crossbar, Clos Net, …) SDVM R site SDVM R site SDVM R site Custom function units can be reconfigured without changing the number of sites Reconfiguring a site: The site to reconfigure drops out of the cluster Some other site controls the partial reconfiguration of the FPGA The SDVM R layer is started on the new softcore The new site joins the cluster M PR PowerPC Hardcore fyfy custom function unit M PR MicroBlaze Softcore M PR MicroBlaze Softcore fzfz custom function unit M PR Softcore type A M PR Softcore type B

14 Professur für Technische Informatik a Slide 14 Klaus Waldschmidt – Dagstuhl April 08 SDVM Test bench Site 1 Site 3 Site 2 Site 4 Ethernet Each site simulates one core of the multi-core chip Cluster consisting of four equal Intel PCs core 1 core 2 core 4core 3

15 Professur für Technische Informatik a Slide 15 Klaus Waldschmidt – Dagstuhl April 08 Another application: Energy Management – contd 1.The parallelism of most applications changes dynamically. 2.The SDVM features: Autonomous scaling Dynamic workload distribution Distributed dynamic scheduling The dynamic scheduling and workload distribution offers new degrees of freedom when choosing an energy management policy. HFMOFF possible EM-state transitions due to workload variation ? HFMLFM OFFLFM HFM SLEEP OFF

16 Professur für Technische Informatik a Slide 16 Klaus Waldschmidt – Dagstuhl April 08 Conclusion The SDVM R … is a virtualization layer for dynamic reconfigurable FPGAs separates the application from the number and type of cores exploits the parallelism and dynamic features of todays FPGAs For further information visit the SDVM´s homepage at

17 Professur für Technische Informatik a Slide 17 Klaus Waldschmidt – Dagstuhl April 08 Thank you for your attention!


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