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A VHDL nyelv alapjai n VHDL nyelvi elvonatkoztatások n Tervezési hierarchiák – szerkezeti leírás.

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Presentation on theme: "A VHDL nyelv alapjai n VHDL nyelvi elvonatkoztatások n Tervezési hierarchiák – szerkezeti leírás."— Presentation transcript:

1 A VHDL nyelv alapjai n VHDL nyelvi elvonatkoztatások n Tervezési hierarchiák – szerkezeti leírás

2 A VHDL nyelv alapjai VHDL nyelvi elemek VHDL is composed of language building blocks that consist of more than 75 reserved words and about 200 descriptive words or word combinations

3 A VHDL nyelv alapjai Foglalt VHDL kulcsszavak VARIABLE WAIT WHEN WHILE WITH XNOR XOR RETURN SELECT SEVERITY SIGNAL SHARED SLA SLL SRA SRL SUBTYPE THEN TO TRANSPORT TYPE UNAFFECTED UNITS UNTIL USE OF ON OPEN OR OTHERS OUT PACKAGE PORT POSTPONED PROCEDURE PROCESS PURE RANGE RECORD REGISTER REM REPORT ROL ROR IN INERTIAL INOUT IS LABEL LIBRARY LINKAGE LITERAL LOOP MAP MOD NAND NEW NEXT NOR NOT NULL DISCONNECT DOWNTO ELSE ELSIF END ENTITY EXIT FILE FOR FUNCTION GENERATE GENERIC GROUP GUARDED IF IMPURE ABS ACCESS AFTER ALIAS ALL AND ARCHITECTURE ARRAY ASSERT ATTRIBUTE BEGIN BLOCK BODY BUFFER BUS CASE COMPONENT CONFIGURATION CONSTANT

4 A VHDL nyelv alapjai Tervleírási módszerek n Szerkezeti leírási módszer n Viselkedési leírási módszer n Adatáramlási leírási módszer n These two are similar in that both use a process to describe the functionality of a circuit Kapcsolási rajz

5 A VHDL nyelv alapjai VHDL nyelvi elvonatkoztatások n VHDL is rich in language abstractions, in addition to which the language can be used to describe different abstraction levels, from functions right down to a gate description n Abstraction levels are a means of concealing details

6 A VHDL nyelv alapjai Elvonatkoztatási szintek n Functional (system) level + architecture => n Behavioral level + resource handler => n RTL (dataflow) level + construction data => n Structural level + technology data => n Logic (gate) level + electrical specification => n Electrical level + layout requirements => n Layout level A fő témánk

7 A VHDL nyelv alapjai n Szerkezeti leírási módszer: expresses the design as an arrangement of interconnected components –It is basically schematic n Viselkedési leírási módszer: describes the functional behavior of a hardware design in terms of circuits and signal responses to various stimuli –The hardware behavior is described algorithmically n Adatáramlási leírási módszer: is similar to a register-transfer language –This method describes the function of a design by defining the flow of information from one input or register to another register or output A leírási módszerek meghatározásai

8 A VHDL nyelv alapjai Feladatköri (rendszer-) szint n Algorithms can be describe at this level n E.g. a controller algorithm can be described and simulated on the computer n An algorithm does not need to contain any time information n Specifications written in VHDL will be able to be simulated

9 A VHDL nyelv alapjai Viselkedési szint n Behavior and time are described at this level n No architecture is required here n The advantage of models at this level is that models for simulation can be built quickly n A behavioral model can be described as functional modules and an interface interface between them n The modules contain one or more functions and time relations n In certain cases the architecture can be defined

10 A VHDL nyelv alapjai A Behavioral Description uses a small number of processes where each process performs a number of sequential signal assignments to multiple signals In contrast, a Data-Flow Description uses a large number of concurrent signal assignment statements A concurrent statement executes asynchronously with respect to other concurrent statements Concurrent statements used in Data-Flow Description include: - block statement (used to group one or more concurrent statements) - concurrent procedure call - concurrent assertion statement - concurrent signal assignment statement Leírási módszerek összehasonlítása

11 A VHDL nyelv alapjai RTL = Regiszter átviteli szint n It consists of a language which describes behavior in –asynchronous and synchronous state machines –data paths –operators (+,*,,...) –registers

12 A VHDL nyelv alapjai Elektromos szint n Other name is: transistor level n There are models of –transistors –capacitances –resistances n This is not supported in VHDL

13 A VHDL nyelv alapjai Layout szint n At layout level models are made of the physical process n This is not supported in VHDL

14 A VHDL nyelv alapjai Szintézis = Növekvő összetettség n Synthesis is done between each level n The volume of information increases between the various abstraction levels –E.g. technology information is required to synthesize from RT to gate level –Each transition (synthesis) generates more information n In order to implement a function in an ASIC, are required the followings: –technology information –wiring information –gate information –set-up times

15 A VHDL nyelv alapjai Miért használnak különböző elvonatkoztatási szinteket? n It is usually the requirements that determine the abstraction level at which the information is to be described n If a short development time is required, a high abstraction level should be chosen as the description language n In practice RT level (and parts of behavioral) can be synthesized automatically to gate level

16 A VHDL nyelv alapjai Különböző alkalmazások n ASIC = Application Specific Integrated Circuit –Usually includes FPGA, gate array, standard cell and full custom designs. n PCB = Printed Circuit Board design –On a circuit board there are usually several ASICs together with a microprocessor and its infrastructure n System = a number of PCBs

17 A VHDL nyelv alapjai Modell kiértékelés n The code for VHDL component can be verified functionally in a simulator n The simulator simulates (“executes”) the VHDL code with input signals and produces a signal diagram and error messages on the basis of the components n The input signals are defined either in VHDL or in the simulator’s language n When the VHDL code is simulated, functional verification takes place n At a later stage, time verification of the design is also possible

18 A VHDL nyelv alapjai Szimuláció n Simulating models is an effective way of verifying the design n The model in the computer is only a time-discrete model, however, while reality is continuous n The computer model is more or less like reality n It is least like reality at a high abstraction level (behavioral) and most like it at the lowest level (layout)

19 A VHDL nyelv alapjai Egyéb elektronikai leíró nyelvek n There are several languages which are used to describe electronic designs n One popular language is called VERILOG n It is used from RT level down n In some other languages there are no hierarchies, which causes major problems when working on complex assignments n There languages are developed by universities and research centers

20 A VHDL nyelv alapjai Other HDL languages n There are several other language extensions built to either aid in RTL construction or assist in modeling: –ParaCore - –RubyHDL - –MyHDL - –JHDL - –Lava - –HDLmaker - –SystemC –AHDL – »It is good for Altera-made chips only, which limits its usefulness »But i t is easy to pick up and use successfully n The main purpose of a language -- programming, hdl, or otherwise -- is to ease the expression of design

21 A VHDL nyelv alapjai A SystemC n C++ könyvtár rendszerszintű modellezésre n Különböző elvonatkoztatási szinteket támogat –Feladatköri leírástól RTL szintűig n Használható gyors, hatékony tervekhez n Igazoláshoz (verification)

22 A VHDL nyelv alapjai Miért nem csak C++? n C++: sorrendi programozás, nem alkalmas párhuzamos események modellezésére n A hardver modellben kell késleltetés, idő n A hardver modellek közlési csatornái (port, signal) különböznek a szoftver modellekben használtaktól n C++ adattípusai túl távol állnak a hardver megvalósításoktól n C++ önmagában nem elég leírni egy bonyolult rendszert

23 A VHDL nyelv alapjai SystemC adattípusok n Adattípusokat határoz meg a hardver modellezéshez –bit (‘0’, ‘1’) –bitvector (‘0101’) –logic (‘0’, ‘1’, ‘Z’, ‘X’) –logicvector (’01XZ’) n Használhatók az alap C++ adattípusok is –fixed –float –signed, unsigned, stb.

24 A VHDL nyelv alapjai Verilog n n Verifying Logic n n Phil Moorby from Gateway Design Automation in 1984 to 1987 – –Absorbed by Cadence » »Cadence 's ownership of Verilog => others support VHDL n n Verilog-XL simulator from GDA in 1986 n n Synopsis Synthesis Tool in 1988 n n In 1990 became open language – –OVI: Open Verilog International n n IEEE Standard in 1995 – –IEEE Std n n Last revision in 2001 – –IEEE Std n n Ongoing work for adding – –Mixed-signal constructs: Verilog-AMS – –System-level constructs: SystemVerilog

25 A VHDL nyelv alapjai VHDL vs. Verilog VHDLVerilog All abstraction levels Complex grammar Easy language Describe a system (everything) Describe a digital system Lots of data types Few data types User-defined package & library No user-defined packages Full design parameterization Simple parameterization Easier to handle large designs Very consistent language. Code written and simulated in one simulator will behave exactly the same in another simulator. E.g. strong typing rules. Less consistent language. If you don't follow some adhoc methodology for coding styles, you will not get it right. It executes differently on different platforms unless you follow some adhoc coding rules.

26 A VHDL nyelv alapjai VHDL vs. Verilog (Cont.) n It does seem that Verilog is easier for designing at the gate-level, but that people who do higher level simulations express a preference for VHDL n VHDL places constraints on evaluation order that limit the optimizations that can be performed –Verilog allows the simulator greater freedom –For example, multiple levels of zero-delay gates can be collapsed into a single super-gate evaluation in Verilog –VHDL requires preserving the original number of delta cycles of delay in propagating through those levels VHDLVerilog In Europe the VHDL is the most popular language Based on Pascal language Based on C language Most FPGA design in VHDL Most ASIC design in Verilog

27 A VHDL nyelv alapjai VHDL vs. Verilog: Process block n n VHDL: process (siga, sigb) begin …... end; n n Verilog: (siga or sigb) begin …. end

28 A VHDL nyelv alapjai VHDL vs. Verilog: Concurrent Signal Assignment n n VHDL: c <= a and b; n n Verilog: assign c = a & b ;

29 A VHDL nyelv alapjai VHDL vs. Verilog: Signal Delays n n VHDL: a <= transport b after 1 ns; n n Verilog: #1 assign a = b; » »‘a’ output is delayed by 1 time unit » »The ‘# ‘ operator is the delay operator » »# N will delay for N simulation units » »Delays can assigned to both inputs and outputs #1 assign a = #1 b; » »‘b’ is delayed by 1 unit, then assigned to ‘a’, which is then delayed by 1 time unit

30 A VHDL nyelv alapjai VHDL vs. Verilog: Clock Generator n n VHDL: signal clk : std_logic := ‘0’; process begin clk <= not (clk) after clkperiod/2; wait on clk; end; n n Verilog: initial clk = 0; always #(clkperiod/2) clk = ~ clk;

31 A VHDL nyelv alapjai Verilog Weakness n n Not well suited for complex, high level modeling – –No user defined type definition – –No concept of libraries, packages, configurations – –No ‘generate’ statement - can’t build parameterized structural models – –No complex types above a two-dimensional array

32 A VHDL nyelv alapjai VHDL vs. Verilog: Managing Large designs n VHDL: –Configuration, generate, generic and package statements all help manage large design structures n Verilog: –There are no statements in Verilog that help manage large designs

33 A VHDL nyelv alapjai VHDL vs. Verilog: Procedures and Tasks n VHDL: –allows concurrent procedure calls n Verilog: –does not allow concurrent task calls

34 A VHDL nyelv alapjai VHDL vs. Verilog: Structural Replication n VHDL: –The generate statement replicates a number of instances of the same design-unit or some sub part of a design, and connects it appropriately n Verilog: –There is no equivalent to the generate statement in Verilog.

35 A VHDL nyelv alapjai Languages “under development” n SystemVerilog –Extending Verilog to higher levels of abstraction for architectural and algorithm design and advanced verification n VHDL 200x –Goal of VHDL Analysis and Standards Group (VASG): »Enhance/update VHDL for to improve performance, modeling capability, ease of use, simulation control, and the type system n e.g.: Data types and abstractions: –variant records –interfaces

36 A VHDL nyelv alapjai Az összetettség csökkentésének módszerei n Language abstractions use the language to describe complex matters without having to describe small details –Functions and procedures are important parts of the language in order to handle complexity n Design hierarchy uses components in order to conceal details - the black box principle –The term black box means that only inputs/outputs of a component are visible at a certain level –It is the designer who decides how many different hierarchies there are to be in the design

37 A VHDL nyelv alapjai Fő sajátságok n VHDL uses the concept of delta delay to keep track of processes that should occur at a given time step, but are actually evaluated in different machine cycles n A delta delay is a unit of time as far as the simulator hardware is concerned, but in the simulation itself time has no advance

38 A VHDL nyelv alapjai VHDL összetevők n Components are a central concept in VHDL n Components are used, among other things, to build up component libraries, e.g.: –microprocessors –special user circuits –other standard circuits n If a “good” component has been designed, it can be saved in a component library, enabling it to be copied as many times as required, i.e. components are reusable –this is called creating instances, i.e. creating the component in a schematic or in the text file

39 A VHDL nyelv alapjai Objektum alapú nyelv n Staying with computer science a while longer, VHDL is an object-based language, i.e. what separates VHDL from object-oriented languages is that the language does not have inheritance n Generic components and instantiation are typical for object-based languages n Generic components are components which can be modified before instantiation, e.g. a generic component which copes with different width for the input and output signals

40 A VHDL nyelv alapjai Feketedoboz használata n The internal structure can be concealed from the designer - the black box principle n In some cases there is no need to know how to component is structured n The designer is usually only interested in – inputs and outputs –a specification function and –access times n The majority of hardware designers are used to working with black boxes such as the 74LSXX circuit family, for example

41 A VHDL nyelv alapjai Fő nyelvi szerkezetek n Tervezési egyed -It is the basic unit of hardware description - = egyed bejelentés + építmény n Egyed bejelentés: fekete doboz modell n Építmény: It describes the relationship between the design entity inputs and outputs Each architecture consists of concurrent statements denoted by CS

42 A VHDL nyelv alapjai Concurrent statements define interconnected processes and blocks that together describe a design’s overall behavior or structure They can be grouped using block statement. Groups of blocks can also be partitioned into other blocks At this same level, a VHDL component (CP) can be connected to define signals within the blocks It is a reference to an entity A process can be a single signal assignment statement or a series of sequential statements (SS) Within a process, procedures and functions can partition the sequential statements Egyidejű és sorrendi utasítások

43 A VHDL nyelv alapjai Elsődleges nyelvi elvonatkoztatás Tervezési egyed Építmény Egyed bejelentés The primary abstraction level of a VHDL hardware model is the Design Entity. The Design Entity can represent a cell, chip, board, or subsystem A Design Entity is composed of two main parts: 1) An Entity Declaration 2) An Architecture

44 A VHDL nyelv alapjai An Entity Declaration defines the interface between the Design Entity and the environment outside of the Design Entity An Architecture describes the relationships between the Design Entity inputs and outputs Elsődleges nyelvi elvonatkoztatás (folyt.)

45 A VHDL nyelv alapjai ENTITY and2 IS PORT (a, b: IN bit; q: OUT bit); END and2; ARCHITECTURE example OF and2 IS -- declaration here BEGIN -- statement here END example; Példa az egyedbejelentésre és az építményre The entity name in the Architecture has to be the same as the identifier of the corresponding Entity Declaration

46 A VHDL nyelv alapjai Egyedbejelentés és építmény n A component is made up of two main parts: –Entity: Port declaration for inputs and outputs –Architecture: structural of behavioural description n Behaviour is defined as a collective name for functions, operations, behaviour and relations n Behaviour can also be a structural description, i.e. the component consists of other components n The entity can be regarded as a black box with inputs and outputs

47 A VHDL nyelv alapjai Példák egyedbejelentésre entity vhdl_component1 is port ( a : in std_logic; port ( a : in std_logic; b : out std_logic); b : out std_logic); end vhdl_component1; entity vhdl_component2 is port ( signal a_in: in std_logic; -- input signal b_out: out std_logic); -- output signal b_out: out std_logic); -- output end vhdl_component2;

48 A VHDL nyelv alapjai Egy építmény példakódja architecture vhdl_code of vhdl_component1 is begin begin B <= not A; B <= not A; end vhdl_code; n Two names are specified in the declaration of the architecture: the component name which describes which entity the architecture belongs to, and vhdl_code, which is the name of the architecture

49 A VHDL nyelv alapjai Az egyedbejelentés jelölésmódja entity is port( [signal] :[ ] ; [signal] :[ ] ); [signal] :[ ] ); end [entity] [ ]; n The word “entity” in the last line is not supported before the VHDL-93 standard

50 A VHDL nyelv alapjai A kapcsok üzemmódjai = in, out, inout, buffer, linkage = in, out, inout, buffer, linkage in: Component only read the signal out: Component only write to the signal inout: Component read or write to the signal (bidirectional signals) buffer: Component write and read back the signal (no bidirectional signals, the signal is going out from the component) linkage: Used only in the documentation

51 A VHDL nyelv alapjai Inout vagy Buffer n Mode inout should only be used in the case of bidirectional signals n If the signal has to be reread, either mode buffer or an internal dummy signal should be used n The word signal is normally left out of the port declaration, as it does not add any information n Mode in and the name of the entity after end can also be left out

52 A VHDL nyelv alapjai Példa az egyszerűsítésre entity gate1 is port( signal a,b: in std_logic; signal c: out std_logic); signal c: out std_logic); end entity gate1; entity gate1 is -- Identical with the above example port( a,b: std_logic; c: out std_logic); c: out std_logic); end;

53 A VHDL nyelv alapjai Építmény n An architecture defines a body for a component entity n An architecture specifies a behavior between inputs and outputs n The architecture name is not the same as the component name: instead an architecture is tied to an entity

54 A VHDL nyelv alapjai Az építmény jelölésmódja architecture of is []begin -- The body of the arch. -- The body of the arch. end [architecture] [ ];

55 A VHDL nyelv alapjai Megjegyzések n The architecture declaration part must be defined before first begin and can consist of, for example: –types –subprograms –components –signal declarations

56 A VHDL nyelv alapjai Egy inverter építménye architecture dtf of cir is begin b_out <= not a_in; b_out <= not a_in; end dtf;

57 A VHDL nyelv alapjai Fontos megjegyzések n An entity can be linked to several architectures such as behavioral and RTL descriptions, for example n Note that VHDL does not differentiate between upper-case and lower-case letters n The double dash “--” indicates that the rest of the line is commentary

58 A VHDL nyelv alapjai A VHDL-ben meghatározott logikai operátorok n NOT n AND n NAND n OR n NOR n XOR n EXOR

59 A VHDL nyelv alapjai Példa a logikai operátorokra architecture rtl of cir is signal int: std_logic; -- Internal signal declaration signal int: std_logic; -- Internal signal declarationbegin int <= not (((a nand b) nor (c or d)) xor e); int <= not (((a nand b) nor (c or d)) xor e); aOut <= int and f; aOut <= int and f; end;

60 A VHDL nyelv alapjai Megjegyzések n Comments follow two hyphens '--' and instruct the analyzer to ignore the rest of the line n There are no multiline comments in VHDL n Tabs improve readability, but it is best not to rely on a tab as a space in case the tabs are lost or deleted in conversion n You should thus write code that is still legal if all tabs are deleted (use spaces as tabs!)

61 A VHDL nyelv alapjai Szövegelemek, pl. rögzített értékű tételek n Sokféle alakú szövegelem létezik a VHDL-ben n A következő kódok néhány példát mutatnak be: entity literals1 is end; architecture bhv of literals1 is begin process variable I1 : integer; variable R1 : real; variable C1 : character; variable S16 : string(1 to 16); variable BV4 : bit_vector(0 to 3); variable BV12 : bit_vector(0 to 11); variable BV16 : bit_vector(0 to 15);

62 A VHDL nyelv alapjai Szövegelemek (folyt.) begin Abstract literals are decimal or based literals -- Abstract literals are decimal or based literals -- Decimal literals are integer or real literals -- Integer literal examples (each of these is the same): I1 := ; I1 := 12e4; I1 := 120_000; -- Based literal examples (each of these is the same): I1 := 2#1111_1111#; I1 := 16#FF#; -- Base must be an integer from 2 to 16: I1 := 16:FFFF:; -- you may use a : instead of # -- Real literal examples (each of these is the same): R1 := ; R1 := 1.2e5; R1 := 12.0E4; -- Character literal must be one of the 191 graphic characters of the 256 ISO Latin-1 set are non-printing control -- characters C1 := 'A'; C1 := 'a'; -- these are different!

63 A VHDL nyelv alapjai Szövegelemek (folyt.) -- String literal examples: S16 := " string" & " literal"; -- concatenate long strings S16 := " string" & " literal"; -- concatenate long strings S16 := """Hello,"" I said!"; -- doubled quotes S16 := """Hello,"" I said!"; -- doubled quotes S16 := %string literal%; -- can use % instead of " S16 := %string literal%; -- can use % instead of " S16 := %Sale: 50% off!!!%; -- doubled % S16 := %Sale: 50% off!!!%; -- doubled % -- Bit-string literal examples: BV4 := B"1100";-- binary bit-string literal BV4 := B"1100";-- binary bit-string literal BV12 := O"7777";-- octal bit-string literal BV12 := O"7777";-- octal bit-string literal BV16 := X"FFFF";-- hex bit-string literal BV16 := X"FFFF";-- hex bit-string literalwait; end process; -- the wait prevents an endless loop end;

64 A VHDL nyelv alapjai Pl. : két bemenet és egy kimenet entity halfAdder is port (x, y : in bit := '0'; sum, cOut : out bit); -- formals end; –Matching the parts of this code with the constructs you can see that the identifier is halfAdder and that corresponds to port_interface_list –Matching the parts of this code with the constructs you can see that the identifier is halfAdder and that x, y: in bit := '0'; sum, cOut: out bit corresponds to port_interface_list –The ports and are formal ports, or formals –The ports x, y, sum, and cOut are formal ports, or formals –This particular entity halfAdder does not use any of the other optional constructs that are legal in an entity declaration

65 A VHDL nyelv alapjai Példa egy félösszeadóra The following architecture body (we shall just call it an architecture from now on) describes the contents of the entity halfAdder : The following architecture body (we shall just call it an architecture from now on) describes the contents of the entity halfAdder : architecture dtf of halfAdder is begin sum <= x xor y; cOut <= x and y; end dtf;

66 A VHDL nyelv alapjai Építmény We use the same signal names, the formals: sum, x, y, and cOut, in the architecture as we use in the entity We use the same signal names, the formals: sum, x, y, and cOut, in the architecture as we use in the entity –we say the signals of the "parent" entity are visible inside the architecture "child" n An architecture can refer to other entity-architecture pairs (i.e., we can nest black boxes) We shall often refer to an entity-architecture pair as entity(architecture) We shall often refer to an entity-architecture pair as entity(architecture) For example, the architecture bhv of the entity halfAdder is halfAdder(bhv) For example, the architecture bhv of the entity halfAdder is halfAdder(bhv)

67 A VHDL nyelv alapjai Kérdés-válasz az építményről Q:Why would we want to describe the outside of a black box (an entity) separately from the description of its contents (its architecture)? A:Separating the two makes it easier to move between different architectures for an entity (there must be at least one). For example, one architecture may model an entity at a behavioral level, while another architecture may be a structural model.


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