1. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 1 Lattice Confidential Low Density GAL

2. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 2 Lattice Confidential Low-Density CMOS PLD Market $M Calendar Year LD CMOS PLD MARKET GROWING AT 7.4% FROM ‘91 TO ‘98

3. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 3 Lattice Confidential Low-Density CMOS PLD Market Share $286M$386M$417M Other AMD Cypress Altera Lattice Other All Others AMD Cypress Altera Alt/Intel Lattice Calendar Year Intel %

4. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 4 Lattice Confidential Market share

5. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 5 Lattice Confidential Semiconductor market

6. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 6 Lattice Confidential PLD market

7. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 7 Lattice Confidential Digital Logic Tutorial

8. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 8 Lattice Confidential Key Poitns •Digital Logic Uses Only Two Values: 1 and 0 •1 and 0 usually represent a voltage •Example –Digital 1 = 5 volts –Digital 0 = 0 volts OR –1 = ON, 0 = Off –1 = True, 0 = False

9. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 9 Lattice Confidential Boolean Basics •Manipulation of digital values is done by Boolean Algebra •Boolean algebra uses primarily AND / OR functions •Boolean equation: TRUE OR FALSE = TRUE •Programmable logic implements the AND / OR functions in hardware

10. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 10 Lattice Confidential Basic Gates •A gate performs a logic function in hardware •Three basic PLD gate types –AND gates –OR gates –Exclusive-OR (XOR) gates •Gates can have any number of inputs

11. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 11 Lattice Confidential AND Gate Example •Output of an AND gate is TRUE only if all inputs are TRUE –In a 2 input gate both switches must be on to turn the light on OFF ON OFF ON OFF ON

12. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 12 Lattice Confidential OFF ON OFF ON Or Gate Example •Output of OR Gate Is TRUE if ANY Input is TRUE –If Either Switch Is ON, The Light Will Trun ON ON

13. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 13 Lattice Confidential XOR Gate Example •Output of XOR Gate Is TRUE Only of One Input Is TRUE –If Only One Switch Is ON, The Light Will Turn ON OFF ON OFF ON OFF

14. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 14 Lattice Confidential Basic Gates Summary SW1 SW2 SW1 SW2 SW1 SW2 Light = SW1 * SW2 Light = SW1 $ SW2 Light = SW1 # SW2 Truth Table (OFF-0, ON-1)

15. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 15 Lattice Confidential PLD Symbols •AND Gate Representations –Traditional Representation –PLD Representation •PLD Connections –Hardwired Connection –Programmed Connection –No Connection Made A B D C Input Terms A B C D

16. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 16 Lattice Confidential Typical PLD Structure Input Terms A B C D Product Terms Output ABCBDABCBD

17. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 17 Lattice Confidential Registers and Clocks •Registers Store a Digital Value •Values Move From Input To Output With Clock Transition •D = Incoming Data •Q = Outgoing Data •CLK = Clock Input; Causes Data Movement D Q CLK

18. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 18 Lattice Confidential Typical GAL Logic Structure Input Terms A B C... Product Terms D Q Feedback Output Enable Registered or Combinatorial

19. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 19 Lattice Confidential Basic GAL Structure Macrocell Gal Macrocell

20. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 20 Lattice Confidential GAL Devices •Low density GAL product families: 16/20V8, 18/22V10/26V12, 20RA10, 20XV10, 6001/6002. Families are organized based on architectural layout and a common Output Logic Macro Cell (OLMC). Pin counts and array sizes are all that change across a family. •Lattice GAL devices have Macro Cell counts from 8 to 39 and package sizes from 20 pins to 28 pins. •All GAL devices have registered or combinatorial options, OE control, and selectable output polarity.

21. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 21 Lattice Confidential GAL Devices •There are also various flavors of each device type. –An L in the product name is a low voltage (3.3V) device. –Zero power devices are either Z or ZD, such as 22LV10ZD. –A VP indicates high drive outputs, such as the 16VP8. –The ispGAL16Z8 was the worlds first ISP PLD. –There is also a Confusion Letter, which roughly indicates the process and technology that the device is based on. •Appended to each device type are speed, power, package, etc. –Device speed grades are by TPD in ns. (HD devices are graded by Fmax in MHz.) –Power dissipation (standard, Low, and Quarter), package type (Pdip, Jlcc, Soic), and Temp/VCC range are appended to device names such as 16LV8C-5LJI for 5nS, low power, PLCC, Industrial.

22. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 22 Lattice Confidential PAL Vs. GAL •PAL: –Programmable Array Logic. –Registers, feedback paths, dynamic I/O, and both output polarities are available. –There are dozens of different devices each with a fixed architecture. For example, a PAL16H2 has 16 inputs and 2 combinatorial outputs each with 8 PTs per OR gate. Output polarity is positive. •GAL: –Generic Array Logic. –GALs are a superset of PALs. A few GAL devices cover all PAL architectures and hundreds of other possible configurations. –GALs add extremely flexible routing and complete reconfigurability. –The structure of GAL devices allows them to replace many PALs with various IO, input and register counts. Therefore, extra programmable areas known as architecture rows are needed for device configuration. There are global configuration modes and well as individual MacroCell options.

23. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 23 Lattice Confidential GAL & PALCE Family World’s Fastest Low Density PLDs

24. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 24 Lattice Confidential GAL16V8

25. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 25 Lattice Confidential GAL16/20V8 OLMC

26. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 26 Lattice Confidential GAL22V10

27. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 27 Lattice Confidential GAL22V10 Family Macrocell

28. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 28 Lattice Confidential ispGAL22V10 and ispGAL22LV10 •In-System Programmable GAL22V10 –7.5ns to 15ns Tpd and 111MHz to 83.3MHz Fmax (5V) –5ns to 15ns Tpd and 200MHz to 83.3MHz Fmax (3.3V) •Standard 22V10 No-Connects Used as ISP Pins •ispGAL Has Same Pin-out as Standard 22V10 –5V Uses Lattice ISP Programming Interface –3.3V Uses ispJTAG Programming Interface ispGAL 22V10 Standard 22V10 28-Lead PLCC 28-Lead SSOP 59% Saving in Area 58% Saving in Height

29. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 29 Lattice Confidential GAL20RA10 •20 Input, 10 Output, Registered, Asynchronous Architecture •High Performance –7.5, 10, 15, 20ns Tpd, 83.3 MHz Fmax •10 Macrocells with Independently Programmable Clocks –Clock Scheme is ideal for Asynchronous Designs GAL20RA10 Functional Block Diagram Output Logic Macrocell Diagram

30. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 30 Lattice Confidential GAL20XV10 •XOR Architecture Makes the GAL20XV10 Ideal for Arithmetic Functions –Counters, Comparators and Decoders –Minimizes Product Term Usage »Equations can be implemented with fewer PTs using XOR than with AND/OR •High Speed and Low Power –10, 15, and 20ns Tpd –90mA Icc Maximum •Replaces Obsolete PAL20L10, 20X10, 20X8, & 20X4 Architectures •Lower Cost Than Alternative 22V10 Solution •Ideal for Graphics, Video, and Multi-Media Applications GAL20XV10 Functional Block Diagram

31. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 31 Lattice Confidential GAL16V8Z/ZD and GAL20V8Z/ZD •High Performance AND Zero Power –12ns Tpd, 83.3 MHz Fmax (AMD @ 18ns) –55mA Icc Active –50 µA Isb Typical (Standby Current) •“Z” Suffix = Input Transition Detection –If No Inputs Switched, Device Will Power down »An Input Transition Will “Wake” the Device –Power Savings Dependent on How Often Inputs Change •“ZD” Suffix = Dedicated Power-Down Pin –Lattice Innovation –Dedicated Pin Controls Power-Down Mode –Designers Can Control Device Power-Down Precisely 16V8Z/ZD Functional Block Diagram

32. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 32 Lattice Confidential ispGDS •In-System Programmable Generic Digital Switch –Tpd = 7.5ns –4-Pin ISP Interface •ispGDS is a Family of ISP Switch Matrices –ispGDS22: 11 x 11 Matrix, 28-Pin DIP/PLCC –ispGDS18: 9 x 9 Matrix, 24-Pin DIP –ispGDS14: 7 x 7 Matrix, 20-Pin DIP/PLCC •Benefits –Reconfigure Systems with Software –Redesign without Hardware Changes –Replaces Multiple DIP Switches •Applications Include –Multiple Clock Source Selection –Dip Switch Replacement –Board Reconfiguration Under Software Control –Signal Routing –Cross-Matrix Switch

33. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 33 Lattice Confidential Low Density 3.3-Volt Products

34. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 34 Lattice Confidential Lattice’s Leadership 3.3 V Low-Density PLD Line GAL16LV8D Low Power Zero Power 25 15 10 3.5 7.5 5 Tpd GAL16LV8ZD GAL20LV8ZD GAL22LV10C GAL16LV8C 3.3 Volt Only 3.3 V and 5V Mixed Voltage { } GAL20LV8D GAL22LV10D GAL22LV10Z/ZD 4 All Speed, Power, Voltage and System Logic Requirements Now Supported!

35. © LATTICE SEMICONDUCTOR CORPORATION Uudet mikropiirit Low Density January 2009 35 Lattice Confidential 22LV10Z/ZD Available for Zero Power 3.3V Applications •15ns Tpd / 71.4 MHz Fmax –Also Available in 25ns Version •Fastest 3.3-Volt, Zero Power PLD in the Industry •“Z” has ITD or Input Transition Detection –If No Input Switched, Device Will Power Down –An Input Transition Will “Wake” the Device •“ZD” Utilizes Dedicated Power Down Pin for Zero-Power –System Controls Power Consumption Directly •Power Consumption (Icc Typ) –50 µA Standby –40 mA Active Zero Power 3.3-Volt GAL22LV10Z/ZD joins the GAL16LV8ZD and GAL20LV8ZD Zero Power 3.3-Volt GAL22LV10Z/ZD joins the GAL16LV8ZD and GAL20LV8ZD