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1/1/ / faculty of Electrical Engineering eindhoven university of technology Memory Management and Protection Part 2: The hardware view dr.ir. A.C. Verschueren.

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Presentation on theme: "1/1/ / faculty of Electrical Engineering eindhoven university of technology Memory Management and Protection Part 2: The hardware view dr.ir. A.C. Verschueren."— Presentation transcript:

1 1/1/ / faculty of Electrical Engineering eindhoven university of technology Memory Management and Protection Part 2: The hardware view dr.ir. A.C. Verschueren Eindhoven University of Technology Section of Digital Information Systems

2 1/1/ / faculty of Electrical Engineering eindhoven university of technology Address translation Not needed for linear memory organisation –Processor generated (logical) address real memory (physical) address –May be handy to attach access rights to addresses Needed for multiple linear address spaces and segmented memories –Complex for multiple linear address spaces the actual address must be checked

3 1/1/ / faculty of Electrical Engineering eindhoven university of technology Table based direct address translation This table grows very large: Translating 1 million addresses with 4 access rights bits requires a 3 MegaByte table! access rights logical address physical address

4 1/1/ / faculty of Electrical Engineering eindhoven university of technology '<' compare '>=' compare Address bounds checking (1) logical address physical address physical offset access rights

5 1/1/ / faculty of Electrical Engineering eindhoven university of technology Address bounds checking (2) Parallel comparators are VERY expensive –Use a lot of power and chip area –Number of address ranges would be limited Physical address ranges must have same sizes as the logical address ranges –Memory which is organised into large (undividable) blocks is hard to manage –Same problem in a purely segmented memory

6 1/1/ / faculty of Electrical Engineering eindhoven university of technology 'page table' logical address Paging (1) bits of the address are not translated: 2 p words in a page have the same access rights access rights physical page logical page offset physical address

7 1/1/ / faculty of Electrical Engineering eindhoven university of technology Paging (2) Paging is cheaper than full address translation –Translating 1 million addresses with 1024 word pages requires a page table with only 1024 entries –With 10 bits physical page numbers and 4 access rights bits, the page table takes less than 2048 bytes! Translating 32 bit addresses with 4096 word pages requires a page table with 1 million entries! –Not all of these pages will be in use at the same time...

8 1/1/ / faculty of Electrical Engineering eindhoven university of technology logical address Second level page table First level page table Multi-level paging 2nd level table present page offset physical address Physical page access rights 2nd level table index 1st level table index

9 1/1/ / faculty of Electrical Engineering eindhoven university of technology Multi-level paging example 4 byte words, 32 bit addresses (2 bits select byte), 1024 word / 4096 byte pages ( = 10+2 bits) –Second level table: 1024 entries( = 10 bits) Entry contains 20 bit physical page number ( = 20), leaves 12 bits for access rights if each entry takes one word Each second level page table fits in one page –First level page table: 1024 entries( = 10 bits) Entry contains 20 bits physical page number of 2nd level table plus the 'table present bit' - fits easily in one word First level page table fits in one page

10 1/1/ / faculty of Electrical Engineering eindhoven university of technology Multi-level paging (continued) This address translation method is very cheap –The example second level table handles 4 MegaByte If code, data and stack fit in 8 MegaByte, we need 3 pages (12 KiloBytes) for translation Multi-level paging is not limited to 2 levels! –Motorola can go up to FIVE levels of tables Each table entry (not just the last) can specify access rights, can also give length limit for next table Searching through 5 tables for each memory access is a bit slow

11 1/1/ / faculty of Electrical Engineering eindhoven university of technology logical address '=' compare Speedup: translation lookaside buffer This 'Content Addressable Memory' lookaside buffer can reach 98% hits with only 32 entries page offset physical address access rights 'hit!' tag

12 1/1/ / faculty of Electrical Engineering eindhoven university of technology logical address A 'set associative' lookaside buffer access rights physical page physical address 'hit!' 'tag' Cheap, simple RAM

13 1/1/ / faculty of Electrical Engineering eindhoven university of technology The problem with set associative buffers A tag clash makes the lookaside buffer worthless –Two or more different pages used in short loop –With same bits but different (tag) bits WaitHereat address 35E6 h DataPortat address 5537 h 4 bit 8 bit 35E WaitHere:JNB DataPort.1,WaitHere Same line in table But different translation tags TWO misses per loop !

14 1/1/ / faculty of Electrical Engineering eindhoven university of technology logical address N-way set associative lookaside buffers Reduce (but do not solve) tag clashes physical page physical address Page table 1 Page table 2 mux 'hit!' hit logic 'tag' Tag table 1 Tag table 2 a.r. 1 a.r. 2 access rights mux set selection Same hit-rate as Content Addressable

15 1/1/ / faculty of Electrical Engineering eindhoven university of technology Lookaside buffer replacement strategy With filled buffer, new translations replace old –With 1-way set associative: bits fix choice! Best choice: remove one which will not be used –Difficult, but Least Recently Used may be the same –LRU requires administration: small choice sets only –Used for N-way set associative lookaside buffers Another strategy: remove one at random –Works well with large choice sets (CAM buffers!) –Small probability of removing the wrong entry

16 1/1/ / faculty of Electrical Engineering eindhoven university of technology logical address Segmented memory address translation Segment table is in main memory ! access rights offset segment 'stack' physical address Segment bases error! ' Segment limits

17 1/1/ / faculty of Electrical Engineering eindhoven university of technology Segmented translation speedup Processor uses only a few segments at once –Place currently used segment info in on-chip registers –Software decides which segments are loaded no replacement strategy needed in hardware! Example: Intel uses 6 current segments –Code, stack and default data –Up to 3 extra data segments referenced explicitly

18 1/1/ / faculty of Electrical Engineering eindhoven university of technology '0' '-1' address space The old-fashioned way: windowing Selection register is normally an output port –Window selection is part of memory management –Should be managed by operating system! window selection register 0 1 N - 2 N - 1 'N' windows mux Expanded Memory 1 1 N - 1


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