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Snapback avoidance design flow for a memory technology Wesley H Kwong Owen W Jungroth Magnolia M Maestre Sean P McDermott Karthik Srikanta Murthy Intel.

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Presentation on theme: "Snapback avoidance design flow for a memory technology Wesley H Kwong Owen W Jungroth Magnolia M Maestre Sean P McDermott Karthik Srikanta Murthy Intel."— Presentation transcript:

1 Snapback avoidance design flow for a memory technology Wesley H Kwong Owen W Jungroth Magnolia M Maestre Sean P McDermott Karthik Srikanta Murthy Intel NVM Solutions Group (TMG-NSG)

2 2 Overview The snapback problem and what is different for NVM Solutions. Flow overview and details. Results, conclusions, and future work.

3 3 Snapback problem Five regions of device operation: –Cutoff, linear, saturation. –Add snapback and failure. High bias conditions on drain and gate nodes initiate problem. Feedback loop power dissipation SNAPBACK

4 4 What is different here? Snapback region is always considered for design of robust ESD protection circuits. –Mitigation strategies well established. Memory technology requires high bias conditions on supporting transistors. –Entire analog portions possibly impacted. Need automated approach to check for snapback. –Up to this point, all approaches are manual.

5 5 Overall flow

6 6 Snapback rule generation Over bias ranges, simulations done to compute I sub. –Impact ionization current and transient induced capacitive currents –Several simulations are run for each circuit and the maximum current level is used to set the risk level. –Current density is then computed: I sub divided by device width. Worst case IR drop is dependent on tap spacing. –A simple worst case model assumes all of the current flows in a straight line from the transistor to the tap without spreading. –The worst case assumes that all transistors in that path are producing their maximum substrate current at the same time. IR drop added to get effective resistance.

7 7 Rule level determination Resistance is categorized into snapback risk levels ( SNPR ) – SNPR = 3 is for the maximum substrate current density and requires a substrate tap next to the transistor. – SNPR = 2 is for medium risk substrate current densities and allows a ~3X greater spacing to the tap. – SNPR = 1 is for low substrate current densities and allows a ~7X greater spacing to the tap. Rules are generated from the above categories. –SOA / assert rules for circuit simulator. SOA / assert compares the current density to the allowed value. –DRC and LVS rules for physical verification tool. LVS checks the that every device gate has the correct SNPR ID layer DRC checks the spacing from SNPR ID layer to substrate tap

8 8 Example rule implementations SOA / assert rules.setsoa label="SOA: NHV ISUB > SNPR=1 Maximum" + M NHV IB(*.B)/(D(*,M)*D(*,W)*0.05)=(- ISNPR1,*).setsoa label="SOA: NHV ISUB > SNPR=2 Maximum" + M NHV IB(*.B)/(D(*,M)*D(*,W)*0.05)=(- ISNPR2,*).setsoa label="SOA: NHV ISUB > SNPR=3 Maximum" + M NHV IB(*.B)/(D(*,M)*D(*,W)*0.05)=(- ISNPR3*((0.6+ABS(VS(*)- VB(*)))/0.6),*) DRC rules snpr3_1tw "snpr3_1tw: If triple nwell device SNPR=3, gate to tap spacing < X" FLATTEN (gate_s3_ntw NOT ptap_pwell_os45) }

9 9 Simulation and schematic annotation Simulation with SOA / assert Include circuit SOA / assert rules. Review violation report Also dump into Excel snpr levels reported. Annotate schematic snpr property

10 10 Layout and physical verification Snapback risk parameter generates recognition layer in pcell. CDL netlist uses snpr property to be recognised by LVS. Tap compliance is checked in DRC, recognition layer correctness checked in LVS. MMLOWVT1 net057 sdin2 sdinb vcc phvlvt m=2 W=75.00u L=12.0u SNPR=2 MMLOWVT0 net056 sdinb sdin2 vcc phvlvt m=2 W=75.00u L=12.0u SNPR=2 Mask layout with snpr layer Netlist with snpr value DRC and LVS check

11 11 Results and conclusions To this point, NO known methodology to check automatically across layout. –Also important as this ties circuit simulation results to layout. Previous reliability history for this technology and predecessors: –Chip 1 (2006): Complete failure of chip at high bias voltages. Failure mechanism ultimately concluded as snapback. –Chip 2 (2010): No failures, but nearly three weeks of manual checking by each team member for snapback violations. –Chip 3 (2012): No failures so far found in design validation, first use of this flow. Minimal impact to tape-in schedule. Flow is deployed for future projects on this technology.

12 12 Future work Work with vendors to expand SOA / assert capabilities in circuit simulators. Improve SOA / assert reporting flows for easier perusal by designers.

13 13 Q&A


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